Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGE (register, D)

Test 1: uops

Code:

  cmge d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371508216872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203716156116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmge d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150620196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010010007101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028489632001820037200371842231876310100200101672002000020037200371110201100991001001000010010007101161119791100001002003820038200382008620038
102042008415061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010010007101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028476802001820037200371842231874510100200100002002034420037200371110201100991001001000010000207101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500779196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500134196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216231978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200542003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001020640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184446187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmge d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150009431968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150027611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500396611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071015211197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000061196874210010101000010100005028476802001820037200371844731878510164201000020203382008420037111002110910101000010000006402162219785010000102003820038200862008520086
1002420037150000088726196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371490000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000103196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmge d0, d8, d9
  cmge d1, d8, d9
  cmge d2, d8, d9
  cmge d3, d8, d9
  cmge d4, d8, d9
  cmge d5, d8, d9
  cmge d6, d8, d9
  cmge d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200381503624525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051141016101020035800001002003920039200392003920039
8020420038150024525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051149169920035800001002003920039200392003920039
80204200381502424525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051149169920035800001002003920039200392003920039
80204200381500245258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511451691020035800001002003920039200392003920039
8020420038150024525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051144165920035800001002003920039200392003920039
8020420038150024525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051144167720035800001002009020039200392003920039
802042003815036245258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511410169920035800001002003920039200392003920039
802042003815024245258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010001511491610920035800001002003920039200392003920039
8020420038150024525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051149169420035800001002003920039200392003920039
8020420038150024525801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051149167720035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)daddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715042039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020141607820035080000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502081608820035080000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502091606820035080000102003920039200392003920039
80024200381501506125800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502081608320035080000102003920039200392003920039
800242003815512010425800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502081608720035080000102003920039200392003920039
8002420038150603925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502051605820035080000102003920039200392003920039
80024200381502703925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502091608520035080000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502061607520035080000102003920039200392003920039
80024200381501503925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502071608620035080000102003920039200392003920039
80024200381500092125800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502051608820035080000102003920039200392003920039