Firestorm: CMGE (zero, 4H) measurements

Code:

  cmge v0.4h, v0.4h, #0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	198	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	1	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	84	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	82	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  cmge v0.4h, v0.4h, #0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	93	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	12	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	4	0	48	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	187	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	3	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	1	1	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	978	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	23	6	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	84	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	44	0	0	640	4	16	5	5	19786	10000	10	20038	20085	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	43	84	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20086
10024	20037	150	0	0	0	0	959	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	44	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	124	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	1094	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	41	0	0	640	4	16	5	4	19786	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  cmge v0.4h, v8.4h, #0
  cmge v1.4h, v8.4h, #0
  cmge v2.4h, v8.4h, #0
  cmge v3.4h, v8.4h, #0
  cmge v4.4h, v8.4h, #0
  cmge v5.4h, v8.4h, #0
  cmge v6.4h, v8.4h, #0
  cmge v7.4h, v8.4h, #0

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20057	150	0	0	938	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	1	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	65	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	32	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	811	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	115	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	29	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	29	25	80108	100	80008	100	80104	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	29	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	92	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	38	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	149	0	0	29	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	29	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	31	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	6	29	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	42	0	1	1	1	5118	0	16	20035	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20051	150	2	0	0	0	751	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	4	16	2	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	2	16	2	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	83	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	1	0	5020	0	4	16	4	2	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	4	16	2	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	2	16	4	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	343	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	2	16	2	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	4	16	4	2	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	33	6	5020	0	2	16	4	2	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	4	16	4	2	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	3	5020	0	2	16	2	4	20035	80000	10	20039	20039	20039	20039	20039

CMGE (zero, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations