Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGE (zero, 4S)

Test 1: uops

Code:

  cmge v0.4s, v0.4s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715000110168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500082168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715000611686251000100010002645211201820372037157131895100010001000203720371110011000001273116111786100020382038203820382038
1004203715001261168625100010001000264521120182037203715713189510001000100020372037111001100001073116111786100020382038203820382038
100420371600061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715002782168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmge v0.4s, v0.4s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715012103196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000204100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000607101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101171119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640616221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020090200372003718443318767100102010000201000020037200371110021109101010000100662216221978610000102003820038200382003820038
10024200371500486119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150096119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715003276119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000106640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmge v0.4s, v8.4s, #0
  cmge v1.4s, v8.4s, #0
  cmge v2.4s, v8.4s, #0
  cmge v3.4s, v8.4s, #0
  cmge v4.4s, v8.4s, #0
  cmge v5.4s, v8.4s, #0
  cmge v6.4s, v8.4s, #0
  cmge v7.4s, v8.4s, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200611500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181160020035800001002003920039200392003920039
8020420038150351502580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204201131500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001011151180160020035800001002003920039200392003920039
8020420038150393292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
802042003815005762580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898022420080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920099

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500003925800101080000108029550640000120019200382003899963100188001020800002080000200382003811800211091010800001003005020081615152009680000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020017161772003580000102003920039200392003920039
800242003815000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000050200171617172003580000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000101300502007161772003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001003005020071617172003580000102003920039200392003920039
800242003815000039258001010800941080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010100050200141617172003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020017161582003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001010005020017167172003580000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000101000502007161772003580000102003920039200392003920039
800242003815006039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000050200171617172003580000102003920039200392003920039