Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGE (zero, 8B)

Test 1: uops

Code:

  cmge v0.8b, v0.8b, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500061168625100010001000264521020222037203715713189510001000100020372037111001100000073216111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715703189510001000100020372037111001100000073116111786100020382038203820382038
100420371610061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150012061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382085
100420371510061168625100010001000264521020182037203715713189510001000100020372037111001100000073116121786100020382038203820382038
100420371500961168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmge v0.8b, v0.8b, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715027611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715042611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500611968625101001001000010010150500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150510611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715018611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000971011611197910100001002003820038200382003820038
102042003715015611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715027611968625101001001000010010000500284752112001820037200371842131874510100200105002001000020037200841110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371506611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001820037200371842131874510100204100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150075061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150021061196862510010101000010101526128487850200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150021061196862510010101000010100005028475210200182003720037184433187671001020100002010000200852003711100211091010100001003640216221978610000102003820038200382003820038
1002420037150090147196862510010101000010100005028475210200182003720037184433187971001020100002010000200372003711100211091010100001063640216221982210000102003820038200382003820038
1002420037150033061196862510010101000010100005028475211200182003720037184438187671001020100002010000200372003711100211091010100001003640216321978610000102003820038200382003820038
100242003715003061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150021061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500990124196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
100242003715000061196862510010101000010100005028475210200182003720037184433188411001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150012061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmge v0.8b, v8.8b, #0
  cmge v1.8b, v8.8b, #0
  cmge v2.8b, v8.8b, #0
  cmge v3.8b, v8.8b, #0
  cmge v4.8b, v8.8b, #0
  cmge v5.8b, v8.8b, #0
  cmge v6.8b, v8.8b, #0
  cmge v7.8b, v8.8b, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)030918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
80204200381500003540292580108100801041008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
8020420038150000150292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
8020420038150000150292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
8020420038150000240292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
8020420038150000210292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
8020420038150000150292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
8020420038150000902925801081008000810080020500640132120019200382003899771299898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039
802042003815000030292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000000360039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020516572003580000102003920039200392003920039
800242003815000000090039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020716752003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020516772003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020516572003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020716772003580000102003920039200392003920039
800242003815000000090039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020516572003580000102003920039200392003920039
800242003815000000060039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020716572003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020516572003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020716772003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005020716752003580000102003920039200392003920039