Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGT (register, 2S)

Test 1: uops

Code:

  cmgt v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073416221787100020382038203820382038
1004203716082168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001168200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmgt v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500126119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000127101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820087
1020420037150039611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150030611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150033611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150018611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150012611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500186611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150015611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500426821968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200841110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000033006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006404162219785010000102003820038200382003820038
100242003715000006006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000009419687251001010100001010000502847680200182003720037184443187671001020100002020000200852013111100211091010100001000000006402162219785010000102003820038200382003820038
100242003715010000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006692162219785010000102003820038200382003820038
10024200371500000216006119687251001010100001010000502847680200182003720037184453187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000015006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000000009419687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000006692162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmgt v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150156119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100207101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010210000100100005002847680120018200372003718436318745101002001000020020000200372003711102011009910010010000100007101161119791100001002008720038200382008620038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150276119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200852003820038
102042003715096119687251010010010000100100005002847680120018200372018218422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150486119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715005124421968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000064410165101978510000102003820038200382003820038
100242003715004526219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000644111610101978510000102003820038200382003820038
1002420037150002621968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000064410161161978510000102003820038200382003820038
100242003714900262196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006441016851978510000102003820038200382003820038
1002420037150002621968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000064451610111978510000102003820038200382003820038
100242003715001826219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000644101610101978510000102003820038200382003820083
10024200371500026219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000644111611111978510000102003820038200382003820038
10024200371500626219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000644101610111978510000102003820038200382003820038
1002420037150002621968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000064410165101978510000102003820038200382003820038
10024200371500626219687251001010100001010000502847680120018200372008418444318767100102010000202000020037200371110021109101010000100000644101610101978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmgt v0.2s, v8.2s, v9.2s
  cmgt v1.2s, v8.2s, v9.2s
  cmgt v2.2s, v8.2s, v9.2s
  cmgt v3.2s, v8.2s, v9.2s
  cmgt v4.2s, v8.2s, v9.2s
  cmgt v5.2s, v8.2s, v9.2s
  cmgt v6.2s, v8.2s, v9.2s
  cmgt v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000876125801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051103161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101162120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001602562003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815001004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001002000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000003051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471510008125800101080000108000050640000102001920038200389996310018800102080000201600002003820038118002110910108000010005020216112003580000102003920039200392003920039
80024200381500003925800101080000128009950640000012001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
800242003815000639258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000106005020116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200979996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
800242003815000273925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039