Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGT (register, 4H)

Test 1: uops

Code:

  cmgt v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468002018203720371571318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000075216111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100015073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100012073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmgt v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500000536196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010046307101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010052307101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010023007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100011407101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150048611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416431978510000102003820038200382003820038
1002420037150092511968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316431978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316341978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416441978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640416441978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416441978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216441978510000102003820038200382003820038
1002420037150005641968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416341978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012006520037200371844431876710010201000020200002003720037111002110910101000010000640316341978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416321978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmgt v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010012115100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715096119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000606402162219785010000102003820038200382003820038
1002420037150000072619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100001206402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010001006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219851010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000005361968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000002161968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010201006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010400306402162219824010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010031006402162219785110000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmgt v0.4h, v8.4h, v9.4h
  cmgt v1.4h, v8.4h, v9.4h
  cmgt v2.4h, v8.4h, v9.4h
  cmgt v3.4h, v8.4h, v9.4h
  cmgt v4.4h, v8.4h, v9.4h
  cmgt v5.4h, v8.4h, v9.4h
  cmgt v6.4h, v8.4h, v9.4h
  cmgt v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051103161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010013051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010030051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000108051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010010051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050206160652003580000102003920039200392003920039
80024200381500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050205160642003580000102003920039200392003920039
80024200381500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050207160552003580000102003920039200392003920039
80024200381500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050205160442003580000102003920039200392003920039
80024200381500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100950205160562003580000102003920039200392003920039
800242003815006092580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050205160662003580000102003920039200392003920039
800242003815093950800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001006650205160562003580000102003920039200392003920039
80024200381500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050204160572003580000102003920039200392003920039
80024200871500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050206160552003580000102003920039200392003920039
80024200381500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000101050204160452003580000102003920100200392003920039