Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGT (register, 4S)

Test 1: uops

Code:

  cmgt v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150821687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160821687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037153821687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150821687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmgt v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720085184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500000536196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000661196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500007261968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100015640216221978510000102003820038200382003820038
1002420037150100611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100057640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000726196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010013640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150002161196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmgt v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100009007102161119791100001002003820038200382003820038
10204200371500000000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100003007101161119791100001002003820085200382003820038
1020420037150000000023519687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000163007101161119791100001002003820038200382003820038
10204200371500000900611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500000000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715000003300611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000042007101161119791100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000081007101161119791100001002003820038200382003820038
102042003715000000004411968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100003007101161119791100001002003820038200382003820038
10204200371510012000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101162119791100001002003820038200382013420038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420085150100317196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020326200372008421100211091010100001000640216221978510000102003820038200382003820038
1002420037150001561196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100123640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmgt v0.4s, v8.4s, v9.4s
  cmgt v1.4s, v8.4s, v9.4s
  cmgt v2.4s, v8.4s, v9.4s
  cmgt v3.4s, v8.4s, v9.4s
  cmgt v4.4s, v8.4s, v9.4s
  cmgt v5.4s, v8.4s, v9.4s
  cmgt v6.4s, v8.4s, v9.4s
  cmgt v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000351103161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019201152003899733999680100200800002001600002003820038118020110099100100800001000651101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000951101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000616640000120019200382003899733999680100200800002001600002003820038118020110099100100800001002051341161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001001051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001001051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001004051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000000039258001010800001080000506400001720019200382003899963100188001020800002016000020038200381180021109101080000100000000050206021644200350080000102003920039200392003920039
8002420038150000060039258001010800001080000506400001620019200382003899963100188001020800002016000020038200381180021109101080000100000000050206051644200350080000102003920039200392003920039
80024200381500000120039258001010800001080000506400001620019200382003899963100188001020800002016000020038200381180021109101080000100000000050206051655200350080000102003920039200392003920039
8002420038150000000039258001010800001080000506400001620019200382003899963100188001020800002016000020038200381180021109101080000100000000050206051655200350080000102003920039200392003920039
8002420038150000000039258001010800001080000506400001520019200382003899963100188001020800002016000020038200381180021109101080000100000000050205031644200350080000102003920039200392003920039
8002420038150000000039258001010800001080000506400001520019200382003899963100188001020800002016000020038200381180021109101080000100000000050205041644200350080000102003920039200392003920039
80024200381500000240039258001010800001080000506400001520019200382003899963100188001020800002016000020038200381180021109101080000100000000050205041633200350080000102003920039200392003920039
80024200381490000120039258001010800001080096506400001520019200382003899963100188001020800002016000020038200381180021109101080000100000000050205031643200350080000102003920039200392003920039
8002420038150000000039258001010800001080000506400001520019200382003899963100188001020800002016000020038200381180021109101080000100000000050205041644200350080000102003920039200392003920039
800242003815000000002292580010108000010800005064000015200192003820038999631001880010208000020160000200382003811800211091010800001000003900050205041634200350080000102003920039200392003920039