Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGT (register, 8B)

Test 1: uops

Code:

  cmgt v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037151386116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111785100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
100420371506116872510001000100026468012018203720371571318951000100020002037203711100110000073116111787100020382038203820382038
1004203715025116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116121785100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203721100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmgt v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071021611197910100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000126071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100010071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100020071011611197910100001002003820038200382023020038
102042008415000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150039919687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006403162219785010000102003820038200382003820038
100242003715008419687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150010319687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500109019687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003714906119687251001010100001010000502847680020018020037200371844431878810010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150052619687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010006402162219786010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010106402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmgt v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500001681968744101001001000010010000500284768012001820037200371842961874010100200100082002001620037200371110201100991001001000010000111718161198020100001002003820038200382003820038
1020420037150009611968725101001001000010010000500284768002001820037200371842961874010100200100082002001620037200371110201100991001001000010000111718161198020100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842961874110100200100082002001620037200371110201100991001001000010000111717161198010100001002003820038200382003820038
10204200371500103311968725101001001000010010000500284768012001820037200371842971874110100200100082002001620037200371110201100991001001000010000111717161198010100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842971874110100200100082002001620037200371110201100991001001000010000111718161198020100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842961874110100200100082002001620037200371110201100991001001000010000111717161198010100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842971874010100200100082002001620037200371110201100991001001000010000111718161198010100001002003820038200382003820038
10204200371500001561968725101001001000010010000500284768002001820037200371842971874110100200100082002001620037200371110201100991001001000010000111717161198010100001002003820038200382003820038
10204200371500001701968725101001001000010010000500284768012001820037200371842961874010100200100082002001620037200371110201100991001001000010000111718161198020100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842961874010100200100082002001620037200371110201100991001001000010000111717161198020100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715001701968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010002006402162219785010000102003820038200382003820038
100242003715001261968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10025200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500841968725100101010000101000050284768002001820037200371844431878510318201000020200002003720037111002110910101000010000006402162419853010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038
10024200371500821968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500821968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmgt v0.8b, v8.8b, v9.8b
  cmgt v1.8b, v8.8b, v9.8b
  cmgt v2.8b, v8.8b, v9.8b
  cmgt v3.8b, v8.8b, v9.8b
  cmgt v4.8b, v8.8b, v9.8b
  cmgt v5.8b, v8.8b, v9.8b
  cmgt v6.8b, v8.8b, v9.8b
  cmgt v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815020124258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
802042003815000230258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000151101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002008920038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392008820039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161220035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039151203925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020171611112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020131612112003580000102003920039200392003920039
8002420038150103925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020121612132003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020111611132003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020131612122003580000102003920039200392003920039
80024200381500010425800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020111613132003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020111612132003580000102003920039200392003920039
8002420038150003925800101080000108010850640000120019200382003899963100188001020800002016000020038200381180021109101080000105020111612112003580000102003920039200392003920039
8002420038149003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020121611122003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020131613122003580000102003920039200392003920039