Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGT (zero, 4S)

Test 1: uops

Code:

  cmgt v0.4s, v0.4s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203716611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037151031686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmgt v0.4s, v0.4s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150002761196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
1020420037150002761196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500027611968625101001001000010010000500284752112001820037200371842117187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
1020420037150000232196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500036536196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
100242003715001986119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150066119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500025119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150066119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150027961196862510010101000010100005028475212001820037200371844319187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150066119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
100242003715002946119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150008419686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmgt v0.4s, v8.4s, #0
  cmgt v1.4s, v8.4s, #0
  cmgt v2.4s, v8.4s, #0
  cmgt v3.4s, v8.4s, #0
  cmgt v4.4s, v8.4s, #0
  cmgt v5.4s, v8.4s, #0
  cmgt v6.4s, v8.4s, #0
  cmgt v7.4s, v8.4s, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420061150632925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150152925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
80204200381502312925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920115
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150242925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
80204200381504442925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150212925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
802042003815002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915001110392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050202163220035080000102003920039200392003920039
8002420038155000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050203163320035080000102003920039200392003920039
80024200381500120392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000050203163220035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050202162320035080000102003920039200392011320039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050202163320035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050203163220035080000102003920039200392003920039
8002420038150030392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050203162320035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050203163320035080000102003920039200392003920039
80024200381500300392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050202163320035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000050202163320035080000102003920039200392003920039