Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGT (zero, D)

Test 1: uops

Code:

  cmgt d0, d0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150821686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371501491686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371515611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371601031686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmgt d0, d0, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000611968625101001001000010010000500284752112001820037200371842861874110100200100082001000820037200371110201100991001001000010000000011171801600198010100001002003820038200382003820038
1020420037150000006119686251010010010000100100005002847521120018200372003718428618740101002001000820010008200372003711102011009910010010000100004106011171801600198000100001002003820038200382003820038
1020420037150003300611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000300000071011611197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000200000071011611197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000120200071011611197910100001002003820038200382003820038
1020420037150120001261968625101001001000010010000500284752102001820037200371842131874510100204100002001000020037200371110201100991001001000010000002000000071012411197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752102001820037200371842131874510100200100002041016420037200371110201100991001001000010020106000073322511197910100001002003820038200382003820038
102042003715000000831968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000200000071011611197910100001002003820038200382003820038
102042017915000900611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
102042003715000000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037149000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006403162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000082196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102012020038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000156196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010101505028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331878810010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmgt d0, d8, #0
  cmgt d1, d8, #0
  cmgt d2, d8, #0
  cmgt d3, d8, #0
  cmgt d4, d8, #0
  cmgt d5, d8, #0
  cmgt d6, d8, #0
  cmgt d7, d8, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200691501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151183161120035800001002003920039200392003920039
80204200381501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151181161220035800001002003920039200392003920039
80204200381501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
802042003815011016625801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151182161120035800001002003920039200392003920090
80204200381501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151181162120035800001002003920039200392003920039
80204200381501102925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
802042003815011029258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010052311151181161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500003925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010010050200216232003580000102003920233200392003920088
80024200381500003925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200316332003580000102003920039200392003920039
80024200381500003925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200316332003580000102003920039200392003920039
80024200381500003925800101080000108000050640724200192003820038999631001880010208000020800002003820038118002110910108000010010050200216332003580000102003920039200392003920039
80024200381500008325800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200216232003580000102003920039200392003920039
80024200381500003925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200316322003580000102003920192200392003920039
800242003815000022925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200316322003580000102003920039200392003920039
80024200381500003925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200316232003580000102003920039200392003920039
80024200381500003925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200316332003580000102003920039200392003920039
80024200381500003925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010000050200316332003580000102003920039200392003920039