Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMHI (register, 4S)

Test 1: uops

Code:

  cmhi v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116211787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371602331687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037159611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmhi v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680020018020037200371842231874510100200100002002000020037200371110201100991001001000010000001177103161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100203007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371490061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715002482196872510100100100001001000050028476801200183200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100001007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150016819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221985110000102003820038200382008520038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150017019687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150012619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150015419687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmhi v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000961196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001002971011611197910100001002003820038200382003820038
1020420037150001284196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001001671011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820086200862003820038
102042003715000094196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720084184223187451010020010000200200002003720037211020110099100100100001002073311611197910100001002003820038200382003820038
102042003715000084196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001001201871011611197910100001002003820038200382003820038
102042003715000084196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003714900061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001002671011611197910100001002003820038200382003820038
1020420037150000145196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150002161196532510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000199571011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)c2cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476801520018200372003718444318767100102010000202000020037200371110021109101010000100006405216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801520018200372003718444318767100102010000202000020037200371110021109101010000100016405216221978510000102003820038200382003820038
100242003715000346196872510010101000010100005028476801520018200372003718444318767100102010000202000020037200371110021109101010000100006405216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800020018200372003718444318767100102010000202000020037200371110021109101010000103006405516221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801520018200372003718444318767100102010000202000020037200371110021109101010000100006405216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800020018200372003718444318767100102010000202000020037200371110021109101010000100006400216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800020018200372003718444318767100102010000202000020037200371110021109101010000100006400216221978510000102003820038200382003820038
10024200371500061196872510022101000010100005028476801520018200372003718444318767100102010000202000020037200371110021109101010000100006405216221978510000102003820038200382003820038
1002420037150039661196872510010101000010100005028476800020018200372003718444318767100102010000202000020037200371110021109101010000100006405216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801520018200372003718444318767100102010000202000020037200371110021109101010000101006405216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmhi v0.4s, v8.4s, v9.4s
  cmhi v1.4s, v8.4s, v9.4s
  cmhi v2.4s, v8.4s, v9.4s
  cmhi v3.4s, v8.4s, v9.4s
  cmhi v4.4s, v8.4s, v9.4s
  cmhi v5.4s, v8.4s, v9.4s
  cmhi v6.4s, v8.4s, v9.4s
  cmhi v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150381040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
802042003815036040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000351101161120035800001002003920039200392003920039
8020420038150312040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815012040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000515258010010080000100800005006400000200190200382003899733999680100200800002001600002003820103118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150297040258010010080000100800005006400000200190200382003899733999680100200801282001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)d9daddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150039258001010800001080000506400000120019200382003899960310018800102080000201600002003820038118002110910108000010005022216401120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899960310018800102080000201600002003820038118002110910108000010005020116201120035080000102003920039200392003920039
8002420038150039258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010165020116201120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899960310018800102080000201600002009620038118002110910108000010005020116201120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899960310018800102080000201600002003820038118002110910108000010005020116201120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899960310018800102080000201600002003820038118002110910108000010005020116301120035080000102003920039200392003920039
80024200381500292258001010800001080000506400000020019200382003899960310018800102080000201600002003820038118002110910108000010005020116701120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899960310018800102080000201600002003820038118002110910108000010005020116311120035080000102003920039200392003920039
8002420038150039258001010800001080000506400001020019200382003899960310018800102080000201600002003820038118002110910108000010005020116301120035080000102003920039200392003920039
8002420038150039258001010800001080000506400000020019200382003899960310018800102080000201600002003820038118002110910108000010005020116201120035080000102003920039200392003920039