Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMHI (register, 8H)

Test 1: uops

Code:

  cmhi v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371509116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmhi v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000251196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100104100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101251119791100001002003820038200382003820038
102042003715000105196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000251196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000168196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500004861196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640616221978510000102003820038200382003820038
100242003715000033661196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000012361196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500003361196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500002761196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500003661196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001002128640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500002161196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmhi v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371490611968725101001001000010010000500284768000200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768001200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003716101061968725101001001000010010000500284768001200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768000200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768001200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371610611968725101001001000010010000500284768000200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715005361968725101001001000010010000500284768001200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371506611968725101001001000010010000500284768001200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197918100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768000200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768000200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371490000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001003406402162219785010000102003820038200382003820038
1002420037150011006119676441002410100121110152502848963120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000006866119687431002211100121010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006404162219785010000102003820038200382003820038
1002420037150000006119687251001212100001210000602847680120018200372003718444318767100102010000202000020037200371110021109101010000100406402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200842003718444318767100122010000202000020037200371110021109101010000100636402162219785010000102003820038200382008520038
1002420037150000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100106402162219785010000102003820038200382003820038
1002420037150000006119687251001012100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100206402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100506402162219785010000102003820038200382003820038
1002420037150000006119687251001212100001010000602847680120018200372003718444318767100102010000202000020037200371110021109101010000100136402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100106405162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmhi v0.8h, v8.8h, v9.8h
  cmhi v1.8h, v8.8h, v9.8h
  cmhi v2.8h, v8.8h, v9.8h
  cmhi v3.8h, v8.8h, v9.8h
  cmhi v4.8h, v8.8h, v9.8h
  cmhi v5.8h, v8.8h, v9.8h
  cmhi v6.8h, v8.8h, v9.8h
  cmhi v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815006125801001008000010080000500640000200192003820038997326999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150016432580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000151101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000251101161120035800001002003920039200392003920039
802042003815001452580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150010425800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000101005020016161462003580000102003920039200392003920039
800242003815008125800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020011166112003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050200101611112003580000102003920039200392003920039
80024200381500104258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050200516582003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050200111613132003580000102003920039200392003920039
800242003815006225800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020012161262003580000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020013161272003580000102003920039200392003920039
800242003815068125800101080000128000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020011161272003580000102003920039200392003920039
8002420038150010922580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502005161162003580000102003920039200392008820039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000101005020091611112003580000102003920039200392003920039