Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMHI (register, D)

Test 1: uops

Code:

  cmhi d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110002073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmhi d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500012619687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500019119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037149006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002008620038200382003820038
10204200371500010319687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500072619687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640316221978510000102003820038200382003820038
10024200371500126119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150036119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150036119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500126119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844412187671001020100002020000200372003711100211091010100001000000640224221978510000102003820038200382003820038
10024200371500276619687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmhi d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715001561196872510100100100001001000050028476800200182003720037184297187411010020010008200200162003720037111020110099100100100001000001117180160019802100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184296187401010020010008200200162003720037111020110099100100100001000001127170160019802100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184296187401010020010008200200162003720037111020110099100100100001000001117170160019802100001002003820038200382003820038
10204200371500279124196872510100100100001001000050028476800200182003720037184297187401010020010008200200162003720037111020110099100100100001000001117170160019801100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184297187411010020010008200200162003720037111020110099100100100001000001117180160019802100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184297187411010020010008200200162003720037111020110099100100100001000001117170160019801100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184296187401010020010008200200162003720037111020110099100100100001000001117390160019802100001002003820038200382003820038
10204200371500061196872510130100100001001000050028476801200182003720037184297187401010020010008200200162003720037111020110099100100100001000001117390160019801100001002003820038200382003820038
1020420084150026461196872510100100100001001000050028476801200182003720037184297187401010020010008200200162003720037111020110099100100100001000001117180160019801100001002008720038200382003820038
1020420037150012103196872510100100100001001000050028476801200182003720037184296187411010020010008200200162003720037111020110099100100100001000001117180160019801100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371501006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200372110021109101010000100230640416331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
100242003715000094319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100060640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010001650640316331978510000102008420038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202033820037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767106202010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100030640316331978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmhi d0, d8, d9
  cmhi d1, d8, d9
  cmhi d2, d8, d9
  cmhi d3, d8, d9
  cmhi d4, d8, d9
  cmhi d5, d8, d9
  cmhi d6, d8, d9
  cmhi d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010001051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381504025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100650200216222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039
8002420038150003925800101380000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039
8002420038150103925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000102350200316442003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100650200217442003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050200216322003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200216422003580000102003920039200392003920039
8002420038150003925801041080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200237232003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200216322003580000102003920039200392003920039