Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMHS (register, D)

Test 1: uops

Code:

  cmhs d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073216111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
100420371527192168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037167261168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715361168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmhs d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037149021611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010067101161119791100001002003820038200382003820038
102042003714900611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010067101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010067101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715009611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010067101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640416221978510000102003820038200382003820038
1002420037150726196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037152611968725100101010000101000050284768012001820037200371844431876710010201000020203362003720037211002110910101000010130640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003714961196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010099640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001020640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmhs d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100001007105161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100002007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150066119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100400007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100001307101161119791100001002003820038200382003820038
1020420037150066119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715000726196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000007507101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000238107101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000016207101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000010307101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010060640216221978510000102003820038200382003820038
10024200371501891968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715010511968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371501891968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371506119687251001010100121010000502847680120018200372003718444318767100102010162202000020037200371110021109101010000103430640216221978510000102003820038200382003820038
10024200371501491968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371501701968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371502601968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371501891968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmhs d0, d8, d9
  cmhs d1, d8, d9
  cmhs d2, d8, d9
  cmhs d3, d8, d9
  cmhs d4, d8, d9
  cmhs d5, d8, d9
  cmhs d6, d8, d9
  cmhs d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815011009872580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110010572580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
80204200381501100292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110915725801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000039311151181161120035800001002003920039200392003920039
8020420038150110066525801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000046300051102162220035800001002003920039200392003920039
802042008815000007102580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100003010200051102162220035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000037300051102162220035800001002003920039200392003920039
802042003815000001472580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051102162220035800001002003920039200392003920039
8020420038150000012425801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000037300051102162220035800001002003920039200392003920039
802042003815000003142580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051102162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)d9ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502015151601111200350080000102003920039200392003920039
8002420038150392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502015101601116200350080000102003920039200392003920039
8002420038150392580010108000010800005064000001200792009820038999631001880010208000020160000200382003811800211091010800001000502015101601111200350080000102003920039200392003920039
8002420038150612580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502015121601013200350880000102003920039200392003920039
8002420038150392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502015111601111200350080000102003920039200392003920039
8002420038150392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502015111601211200350080000102003920039200392003920039
8002420038150392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502015111601511200350080000102003920039200392003920039
8002420038150392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502015101601211200350080000102003920039200392003920039
8002420038150704258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100050201591601112200350080000102003920039200392003920039
80024200381504422580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502015111601111200350080000102003920039200392003920039