Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMLE (zero, 2D)

Test 1: uops

Code:

  cmle v0.2d, v0.2d, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716000006116862510001000100026452102018203720371571318951000100010002037203711100110004073116111786100020382038203820382038
1004203715000006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371500100611686251000100010002645210201820372037157131895100010001000203720371110011000015973116111786100020382038203820382038
1004203715000006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715000006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715000006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715000006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715100006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715000006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716000006116862510001000100026452102018203720371571318951000100010002037203711100110003373116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmle v0.2d, v0.2d, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000210196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500020761196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000207102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150000126196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000082196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150000168196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150000124196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500027145196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
100242003715000166196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640316341978610000102003820038200382003820038
100242003715000251196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371509061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371500061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmle v0.2d, v8.2d, #0
  cmle v1.2d, v8.2d, #0
  cmle v2.2d, v8.2d, #0
  cmle v3.2d, v8.2d, #0
  cmle v4.2d, v8.2d, #0
  cmle v5.2d, v8.2d, #0
  cmle v6.2d, v8.2d, #0
  cmle v7.2d, v8.2d, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571500000732580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150005310292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181160020035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161020035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181160020035800001002003920039200392003920039
802042003815000008392580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000010132580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180161120035800001002003920039200392003920039
802042003815000007072580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500000502580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020416242003580000102003920039200392003920039
80024200381500422258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020616352003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020516362003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020616622003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010205020316622003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020616242003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020616422003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020716752003580000102003920039200392003920039
8002420038150083258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010035020616422003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631004580010208000020800002003820038118002110910108000010005020416242003580000102003920039200392003920039