Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMLE (zero, 2S)

Test 1: uops

Code:

  cmle v0.2s, v0.2s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073316221786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715012611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371509611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073216221786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmle v0.2s, v0.2s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371501115346196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001001071001161119791100001002003820038200382003820038
10204200371490111761196862510120130100001001000050028475210200182003720084184213187451010020010000200100002003720037111020110099100100100001000071001161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000056628487850200182003720037184213187451010020010000200100002003720037111020110099100100100001000071001161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001001071001161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001001471001161119825100001002003820038200382003820038
102042008515100061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071001161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071001161119791100001002003820038200382003820038
10204200371500021061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071001161119791100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200222003720037184213187631010020010000200100002003720037111020110099100100100001000071001161119791100001002003820038200382003820038
10204200371500039061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071001161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000120061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
100242003714900003330061196862510010101000010100005028475211200542003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
100242003715000002400251196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100221091010100001000000006402162219786010000102003820038200382003820038
10024200371500000420061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402754219786010000102003820038200382003820038
10024200371500000000124196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371500000360061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmle v0.2s, v8.2s, #0
  cmle v1.2s, v8.2s, #0
  cmle v2.2s, v8.2s, #0
  cmle v3.2s, v8.2s, #0
  cmle v4.2s, v8.2s, #0
  cmle v5.2s, v8.2s, #0
  cmle v6.2s, v8.2s, #0
  cmle v7.2s, v8.2s, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591500005129258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039
8020420038150000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039
8020420038150000329258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039
8020420038150000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039
8020420038150000629648010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039
8020420038150000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000211151181600200350800001002003920039200392003920135
8020420038150000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039
8020420038150000050258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039
8020420038150000057258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000211151181600200350800001002003920039200392003920039
8020420038151000050258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151181600200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500003007042580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020616762003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020616562003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020816562003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020516752003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996710018800102080000208000020038200381180021109101080000100005020616562003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020516562003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020716872003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020816852003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020816562003580000102003920039200392003920039
8002420038150000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020516872003580000102003920039200392003920039