Firestorm: CMLE (zero, 8H) measurements

Code:

  cmle v0.8h, v0.8h, #0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	2	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	82	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	82	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  cmle v0.8h, v0.8h, #0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	147	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	24	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	89	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	812	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	0	20037	20037	18443	3	18785	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	71	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	44	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19686	44	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  cmle v0.8h, v8.8h, #0
  cmle v1.8h, v8.8h, #0
  cmle v2.8h, v8.8h, #0
  cmle v3.8h, v8.8h, #0
  cmle v4.8h, v8.8h, #0
  cmle v5.8h, v8.8h, #0
  cmle v6.8h, v8.8h, #0
  cmle v7.8h, v8.8h, #0

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20057	150	1	0	0	29	25	80108	100	80008	100	80020	500	640132	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	1	1	1	5118	2	16	1	2	20035	80000	100	20049	20049	20049	20049	20049
80204	20049	151	0	0	0	64	26	80116	100	80016	100	80028	500	640196	20028	20049	20048	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5128	3	23	2	3	20046	80000	100	20049	20049	20049	20049	20049
80204	20048	150	0	0	0	64	27	80116	100	80016	100	80028	500	640196	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20049	20048	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5129	1	23	3	4	20045	80000	100	20049	20049	20049	20049	20049
80204	20049	150	0	0	0	254	26	80116	100	80016	100	80028	500	640196	20028	20048	20086	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5129	2	23	3	2	20045	80000	100	20050	20049	20049	20049	20049
80204	20049	150	0	0	0	64	27	80116	100	80016	100	80028	500	640196	20028	20049	20049	9976	10	9986	80128	200	80038	200	80038	20048	20049	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5128	2	23	2	3	20045	80000	100	20049	20050	20050	20049	20050
80204	20048	150	0	0	0	64	26	80116	100	80016	100	80028	500	640196	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20049	20049	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5128	2	23	3	3	20045	80000	100	20049	20049	20049	20049	20050
80204	20049	150	0	0	0	64	27	80116	100	80016	100	80028	500	640196	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20049	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5128	2	23	2	3	20045	80000	100	20049	20049	20050	20049	20049
80204	20049	150	0	0	0	64	26	80116	100	80016	100	80028	500	640196	20028	20049	20049	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	1	0	2	2	2	5128	2	23	3	2	20046	80000	100	20049	20049	20049	20049	20049
80204	20048	150	0	0	0	64	26	80116	100	80016	100	80028	500	640196	20028	20049	20049	9976	9	9986	80128	200	80038	200	80038	20049	20049	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5128	3	23	3	2	20046	80000	100	20049	20049	20049	20049	20049
80204	20048	150	0	0	0	64	27	80116	100	80016	100	80028	500	640196	20028	20049	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	2	2	2	5128	3	23	2	2	20046	80000	100	20049	20050	20049	20050	20050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	150	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	4	16	5	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	324	25	80010	10	80000	10	80000	50	640000	0	20079	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	5	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	5	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	5	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	15	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	3	16	5	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5037	5	16	3	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	3	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	3	5020	3	16	3	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	6	16	5	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	6	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	5	16	5	5	20035	80000	10	20039	20039	20039	20039	20039

CMLE (zero, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations