Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMTST (register, 2S)

Test 1: uops

Code:

  cmtst v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715017016872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715010316872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmtst v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100069007102161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000117007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000126119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100099207102251119791100001002008520038200382003820038
102042003715000126119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100096007101161119791100001002003820038200382003820038
10204200371500006341968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100099007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100081007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100093007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150007261968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221982310000102003820038200382003820038
1002420037150021611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820133203242032320366

Test 3: Latency 1->3

Code:

  cmtst v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500096119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150002461196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000710348221996931100001002003820038200382003820275
10204202301520006119687251010011410060100100005002847680020018200372003718422318745101002021000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500038219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100371011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611198620100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150025119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251002310100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150020819687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150078919687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150014519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001012100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmtst v0.2s, v8.2s, v9.2s
  cmtst v1.2s, v8.2s, v9.2s
  cmtst v2.2s, v8.2s, v9.2s
  cmtst v3.2s, v8.2s, v9.2s
  cmtst v4.2s, v8.2s, v9.2s
  cmtst v5.2s, v8.2s, v9.2s
  cmtst v6.2s, v8.2s, v9.2s
  cmtst v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004715004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
802042003815704025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150124025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101271120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004052801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051261161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150020392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050206164220035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050204162420035080000102003920039200392003920039
800242003815000333392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162420035080000102003920039200392003920039
8002420038156000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050204164220035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162420035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050204164220035080000102003920039200392003920039
80024200381500001342580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050204164220035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162420035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050204164220035080000102003920039200392003920039
80024200381500021392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100000050202162420035080000102003920039200392003920039