Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMTST (register, 8H)

Test 1: uops

Code:

  cmtst v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038208520382038
10042037150611687251000100010002646802018203720371572318951152100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371560611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmtst v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150000012419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715000008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715000008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100073511611197910100001002003820038200382003820038
102042003715000008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715000008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611198330100001002003820038200382003820038
1020420037150000033919687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150000010319687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500001241968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038
10024200371500001661968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038
10024200371500002321968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038
10024200371500001661968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200862003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmtst v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000821968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003715000030611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003714900000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
10204200371500003264611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150000001561968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010100640416221978510000102003820038200382003820038
100242003715009611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010100640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200841844417187671001022103262020000200372003711100211091010100001011020640216221978510000102003820038200382003820038
100242003715009611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010060640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100840640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100151640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010060640216221978510000102003820038200382003820038
1002420037150007261968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmtst v0.8h, v8.8h, v9.8h
  cmtst v1.8h, v8.8h, v9.8h
  cmtst v2.8h, v8.8h, v9.8h
  cmtst v3.8h, v8.8h, v9.8h
  cmtst v4.8h, v8.8h, v9.8h
  cmtst v5.8h, v8.8h, v9.8h
  cmtst v6.8h, v8.8h, v9.8h
  cmtst v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200481504414025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001001000511041654200350800001002003920039200392003920039
80204200381504264025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001001000511041644200350800001002003920039200392003920039
80204200881502740258010010080000106800005006400000200582003820038997339996801002008000020016000020038201031180201100991001008000010000025110416352007925800001002003920039201032003920039
80204200901504088225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000090511051645200350800001002003920039200392003920039
80204200381493424025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511051654200350800001002003920039200392003920039
802042003815064025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001001000511051654200350800001002003920039200392003920039
80204200381503634025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511051645200350800001002003920039200392003920039
8020420038150216125801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511041655200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511051645200350800001002003920039200392003920039
8020420038150184025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511051645200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391503927052580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241516016132003580000102003920039200392003920039
800242003815002402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241216014122003580000102003920039200392003920039
800242003815002402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241516014172003580000102003920039200392003920039
8002420038150441240608001012800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100005027151601382003580000102003920039200392003920039
8002420038150182402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241616016162003580000102003920039200392003920039
8002420038150362402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241716014162003580000102003920039200392003920039
80024200381503332402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241616016162003580000102003920039200392003920039
800242003815002402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050271616015122003580000102003920039200392003920039
800242003815002402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241516013162003580000102003920039200392003920039
800242003815002402580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000050241616014162003580000102003920039200392003920039