Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DUP (element, scalar, H)

Test 1: uops

Code:

  dup h0, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371502621686251000100010002645212018203720371571318951000100010002037203711100110000077516551786100020382038203820382038
100420371502621686251000100010002645212018203720371571318951000100010002037203711100110000077516561786100020382038203820382038
100420371502831686251000100010002645212018203720371571318951000100010002037203711100110000377516551786100020382038203820382038
100420371502851686251000100010002645212018203720371571318951000100010002037203711100110000077516551786100020382038203820382038
1004203715021061686251000100010002645212018203720371571318951000100010002037203711100110000077516551786100020382038203820382038
1004203715026216862510001000100026452120182037203715713189510001000100020372037111001100001277516551786100020382038203820382038
100420371532621686251000100010002645212018203720371571318951000100010002037203711100110000077516551786100020382038203820382038
100420371602831686251000100010002645212018203720371571318951000100010002037203711100110000077516551786100020382038203820382038
1004203716021041686251000100010002645212018203720371571318951000100010002037203711100110000077516551786100020382038203820382038
100420371502621686251000100010002645212018203720371571318951000100010002037203711100110000077516551786100020382038203820382038

Test 2: Latency 1->2

Code:

  dup h0, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010043607101161119791100001002003820038200382003820038
1020420037150006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100416507101161119791100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001001017707101161119791100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000307101161119791100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000607101161119791100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715001261196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000607101161119791100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000307101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000003064031633197860210000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000064031633197860010000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100004403064031633197860010000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000064031633197860010000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000064031633197860010000102003820038200382003820038
1002420037150002141968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000003064031633197860010000102003820038200382003820038
100242003715600611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000064031633197860010000102003820038200382003820038
100242003715000821968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000064031633197860010000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000064031633197860010000102003820038200382003820038
100242003715000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000064031633197860010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  dup h0, v8.h[1]
  dup h1, v8.h[1]
  dup h2, v8.h[1]
  dup h3, v8.h[1]
  dup h4, v8.h[1]
  dup h5, v8.h[1]
  dup h6, v8.h[1]
  dup h7, v8.h[1]
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815000182925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010036311151181160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500004092580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001311151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001005011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015039258001010800001080000506400002001920038200389996310018802042080000208000020038200381180021109101080000100130502017165162003580000102003920039200392003920039
800242003815039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100100502016166162003580000102003920039200392003920039
800242003815039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100100502016166162003580000102003920039200392003920039
8002420038150392580010108000010800005064000020019200382003899963100188001020800002080000200382003811800211091010800001000005020161616162003580000102003920039200392003920039
8002420038150392580010108000010800005064075620019200382003899963100188001020800002080000200382003811800211091010800001000005020161616162003580000102003920039200392003920039
80024200381503925800101080000108000050640000200192003820038999631001880010208000020800002003820038118002110910108000010017005020161616162003580000102003920039200392003920039
800242003815039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100213430502016166162003580000102003920039200392003920039
800242003815039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100024050206161662003580000102003920039200392003920039
800242003815039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100030502016166162003580000102003920039200392003920039
800242003815039258001010800001080000506400002001920038200389996310018800102080000208000020038200381180021109101080000100000502016161662003580000102003920039200392003920039