Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DUP (element, vector, 16B)

Test 1: uops

Code:

  dup v0.16b, v0.b[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100012073216221786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715010316862510001000100026452102018203720371571318951000100010002037203711100110000073216221786100020852085203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100008773216221786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073216221786100020382038203820382038
1004203715246116862510001000100026452102018203720371571318951000100010002037203711100110000973216221786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073216221786100020382038203820382038

Test 2: Latency 1->2

Code:

  dup v0.16b, v0.b[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500110124196862510100100100001001000050028475212001820037200861842431874510125200100002001000020037200371110201100991001001000010002020710116111979125100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451012520010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071211611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071021611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011711197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000014519686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640216431978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001080640416431978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640416341978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640416341978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640316341978610000102003820038200382003820038
10024200371501893519686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640316341978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521200182003720037184433187791001020100002010000200372003711100211091010100001000640416431978610000102003820038200382003820038
1002420037150072619686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001013640316431978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640416441978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521200182003720037184433187671001020100002010000200372003711100211091010100001000640417341978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  dup v0.16b, v8.b[1]
  dup v1.16b, v8.b[1]
  dup v2.16b, v8.b[1]
  dup v3.16b, v8.b[1]
  dup v4.16b, v8.b[1]
  dup v5.16b, v8.b[1]
  dup v6.16b, v8.b[1]
  dup v7.16b, v8.b[1]
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150102925801081028000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500021925801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500127125801081008000810080020500640132020019020038200389977699898012020080032200801362003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
802042003815001211325801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420090150002925801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150002925801081008000810080020500640756020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180163120035800001002003920039200392003920039
80204200381500050425801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
80204200381500011325801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020416422003580000102003920039200392003920039
8002420038155003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020416422003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020216242003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200992003899963100188001020800002080000200382003811800211091010800001000005020216432003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020416342003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020216242003580000102003920039200392003920039
80024200381500051425800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000005020416242003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020416242003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000015020416242003580000102003920039200392003920039
8002420038150006025800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000005020416442003580000102003920039200392003920039