Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DUP (element, vector, 2D)

Test 1: uops

Code:

  dup v0.2d, v0.d[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715001431686251000100010002645212018203720371571318951000100010002037203711100110000075116111786100020382038203820382038
1004203715001561686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716001671686251000100010002645212018203720371571318951000100010002037203711100110000075116111786100020382038203820382038
1004203715001431686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820862038
100420371503611686251000100010002645212018203720371570318951000100010002037203711100110000375116111786100020382038203820382038
100420371600611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716001431686251000100010002645212018203720371571318951000100010002084203711100110000073116111786100020382038203820382038
100420371500611686251000100010002645212018203720371571318951000100010002037203711100110000075116111786100020382038203820382038
1004203715001681686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  dup v0.2d, v0.d[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150019119686251011410010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
1020420037150016819686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715008219686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521200182003720088184253187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500147196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000010710116111979127100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000640516221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100103640316221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372008418443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037155036119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500017819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100100640316221978610000102003820038200382003820038
10024200371500910319686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  dup v0.2d, v8.d[1]
  dup v1.2d, v8.d[1]
  dup v2.2d, v8.d[1]
  dup v3.2d, v8.d[1]
  dup v4.2d, v8.d[1]
  dup v5.2d, v8.d[1]
  dup v6.2d, v8.d[1]
  dup v7.2d, v8.d[1]
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038150002925801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151182162220035800001002003920039200392003920039
8020420038150102925801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151181161220035800001002003920039200392003920039
80204200381500034325801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151181162220035800001002003920039200392003920039
8020420038150005725801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151182161220035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151182161120035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151181161220035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151181162220035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151182162120035800001002003920039200392003920039
80204200381500011325801081008000810080020500640132020019020038200389977699898012020080032200800322003820038118020110099100100800001000011151181162220035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001000011151182161220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd2d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150000000000104258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502011216211820035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502002316202520035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502002716252520035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200782009820038999631001880010208000020800002003820038118002110910108000010000000502002016252020035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502002116252020035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502002516252420035080000102003920039200392003920039
8002420038150000000000102258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502001916242220035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502002516252320035080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000012001920038200381000431001880010208000020800002003820038118002110910108000010000000502002416242320035080000102003920039200392003920039
800242003815000000000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000000502002516251520035080000102003920039200392003920039