Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DUP (element, vector, 2S)

Test 1: uops

Code:

  dup v0.2s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150821686251000100010002645212018203720371571318951000100010002037203711100110000073216111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037160611686251000100010002645212018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
10042037166611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110003073116111786100020382038203820382038
10042037163611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371501051686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100210000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  dup v0.2s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001002071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000062628475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720085111020110099100100100001004117171011611197910100001002003820038200382003820038
10204200371500061196862510125100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011621197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000007619686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000001326402162219786010000102008620086200382003820038
1002420037150000000006119686251001010100001010000502847521020018200372003718443318767100102010000201016820037200841110021109101010000100002006402162219786010000102003820085200382003820038
1002420037150000000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000000006119686251002210100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000000025119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000000015619686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  dup v0.2s, v8.s[1]
  dup v1.2s, v8.s[1]
  dup v2.2s, v8.s[1]
  dup v3.2s, v8.s[1]
  dup v4.2s, v8.s[1]
  dup v5.2s, v8.s[1]
  dup v6.2s, v8.s[1]
  dup v7.2s, v8.s[1]
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151183163320035800001002003920039200392003920039
80204200381500029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151183163320035800001002003920039200392003920039
80204200381500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151183163420035800001002003920039200392003920039
80204200381500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151183163420035800001002003920039200392003920039
80204200911500029258010810080008100800205006401321200192003820038997769989801202008013720080032200382003811802011009910010080000100020011151183164320035800001002003920039200392003920039
80204200381500029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151183163420035800001002003920039200392003920039
80204200381500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151182164420035800001002003920039200392003920039
80204200381500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151184163420035800001002003920039200392003920039
8020420038150001264258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151183164420035800001002003920039200392003920039
80204200381500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000011151183164320035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511506025800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000502017160642003580000102003920039200392003920039
80024200381503242580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100050206160532003580000102003920039200392003920039
8002420038150392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100050203160532003580000102003920039200392003920039
80024200381507502580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100950206160642003580000102003920039200392003920039
80024200381503925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001001550205160542003580000102023920039200392003920039
8002420038150392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100050205160662003580000102003920039200392003920039
80024200381503925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000502012160562003580000102003920039200392003920039
800242003815010425800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001001250205160642003580000102003920039200392003920039
80024200381503925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001020502051606112003580000102003920039200392003920039
8002420088150392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100050205160662003580000102003920039200392003920136