Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DUP (element, vector, 4H)

Test 1: uops

Code:

  dup v0.4h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150010516862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150061168625100010001000264521020182037203715713189510001000100020372037111001100030073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  dup v0.4h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371490006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820180
10204200371490006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521200182008520085184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500006119686251010010010000104100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
1020420037150017706119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382013220038
10204200371500006119686251010010010000100100005002847521200652003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197919100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000000671011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000000710116111985721100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150053619686251001010100001010000502847521120018020037200371844303187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844303187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
10024200371500104019686251001010100001010000502847521020018020037200371844303187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200371844303187671001020100002010000200372003711100211091010100001020640316331978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200371844303187671001020100002010000200372003711100211091010100001056640316331978610000102003820038200382003820038
1002420037150010319686251001010100001010000502847521020018020037200371844303187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200371844303187671001020100002010000200372003711100211091010100001010640316331978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200371844303187671001020100002010000200372003711100211091010100001000640316331978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200371844303187671001020100002010000200372003711100211091010100001010640316331978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200851844303187671001020100002010168200862003711100211091010100001000640316331978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  dup v0.4h, v8.h[1]
  dup v1.4h, v8.h[1]
  dup v2.4h, v8.h[1]
  dup v3.4h, v8.h[1]
  dup v4.4h, v8.h[1]
  dup v5.4h, v8.h[1]
  dup v6.4h, v8.h[1]
  dup v7.4h, v8.h[1]
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005715092925801081008000810080020500640132120019020038200389977699898012020080032200800322003820038118020110099100100800001004400111511801620035800001002003920039200392003920039
802042003815024292580108100800081008002050064013202001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815015292580108100800081008002050064013202001902003820038997769989801202008014220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001932003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815027292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015000012039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010050205164320035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010050204164220035080000102003920039200392003920039
80024200381500001539258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010050204164220035080000102003920039200392003920039
80024200381500003939258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010050204164220035080000102003920039200392003920039
8002420038150000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010050204164420035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010050204162420035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010050204164320035080000102003920039200392003920039
80024200381500006339448010210800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010050205164420035080000102003920039200392003920039
800242003815000044739258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010050205164220035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010050202164220035080000102003920039200392003920039