Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DUP (element, vector, 4S)

Test 1: uops

Code:

  dup v0.4s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073316331786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073216331786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073216331786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073316331786100020382038203820382038
100420371500821686251000100010002645211201820372037157131895100010001000203720371110011000012073316331786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073316331786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073316331786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073316321786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073316331786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073316321853100020382038203820382038

Test 2: Latency 1->2

Code:

  dup v0.4s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150001491968625101001001000010010000626284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000000710116111979125100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071211611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
1020420037150004911968625101001001000010010000626284752112001820037200371842131874510100200100002001000020084200371110201100991001001000010000000710116221979125100001002003820038200382003820038
102042003715000126196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000166196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715000191196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715001261968625100101010000101000050284752102006620037200371844331876710010201000020100002003720037111002110910101000010000640316221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715001241968625100241010012101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221985410000102003820038200382003820038
100242003715005081968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200862003820038
10024200371500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715001451968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010010640216221978610000102003820038200382003820038
10024200371490611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  dup v0.4s, v8.s[1]
  dup v1.4s, v8.s[1]
  dup v2.4s, v8.s[1]
  dup v3.4s, v8.s[1]
  dup v4.4s, v8.s[1]
  dup v5.4s, v8.s[1]
  dup v6.4s, v8.s[1]
  dup v7.4s, v8.s[1]
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150101000015025801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511851653200350800001002003920039200392003920039
802042003815010100002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511841644200350800001002003920039200392003920039
802042003815010100002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511841665200350800001002003920039200392003920039
802042003815010100005025801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511841653200350800001002003920039200392003920039
802042003815010100002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511851655200350800001002003920039200392003920087
802042003815010100002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511851744200350800001002003920039200392003920039
802042003815010100002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010003111511841643200350800001002003920039200392003920039
802042003815010100002925801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511841645200350800001002003920039200392014620039
802042003815010100009625801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511851655200350800001002003920039200392003920039
8020420038150101000051525801081008000810080020500640132020019200382003899776998980120200800322008003220038200381180201100991001008000010000111511851665200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150006025800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100010050205163352003580000102003920039200392003920039
8002420038150003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100003050203163352003580000102003920039200392003920039
80024200381500060925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100003050205163532003580000102003920039200392003920039
8002420038150001482580010108000010800005064000000200192003820038999681004580010208000020800002009020038118002110910108000010400518050205163532003580000102003920039200392003920039
8002420038150006225800101080000108000050640000302001920038200381000531001880010208009720800002003820038118002110910108000010231465050205163552003580000102003920039200392003920039
80024200381500014825800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050205163552003580000102003920039200392003920039
80024200381500051425800101080000108000050640000012001920038200389996310018800102080000208000020038200381180021109101080000100000050205164532003580000102003920039200392003920039
80024200381500014825800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050203164532003580000102003920039200392003920039
80024200381500039125800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050205164552003580000102003920039200392003920039
8002420038150008125800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000650205165552003580000102003920039200392008920039