Firestorm: DUP (general, 16B) measurements

Code:

  dup v0.16b, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	375	2	1	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	0	360	2	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	1	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	376	72	3	108	2000	1000	1000	1000	1000	375	379	1	1	1001	1000	1000	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	3	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	380	3	0	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	379	375	1	1	1001	1000	1000	0	75	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	2	0	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	1	16	1	1	377	1000	1000	376	376	376	376	376
2004	375	2	0	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	378	1	1	1001	1000	1000	0	75	1	16	1	2	372	1000	1000	376	376	376	377	376
2004	375	2	1	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.16b, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120036	899	0	120017	109457	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116243	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1	0	0	1310	1	3	24	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	12	120020	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120033	115525	3	116240	30100	200	10000	20000	200	10000	20000	120033	120032	1	1	20201	100	99	100	10100	10000	100	0	10006	5	2	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120034
30204	120032	899	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120040	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	2	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	10	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	705	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10065	20000	200	10000	20000	120075	120033	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	2	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20121	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5739080	13693452	1	120013	0	120032	120032	115548	3	116262	30336	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	0	0	120017	109491	25	40010	10010	20005	10000	10	20000	10000	50	5736440	13670029	0	120013	3	120065	120034	115548	3	116262	30010	20	10062	20000	20	10000	20000	120073	120079	1	1	20021	10	9	10	10010	10000	10	10000	0	0	135	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120051	899	0	0	0	0	0	120017	109456	25	40019	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120067	115550	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	189	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120068	899	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	72	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120058	120033	120033	120033	120033
30024	120060	899	0	0	0	0	0	120017	109517	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	114	0	1270	1	16	1	1	119577	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120033	899	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20456	10000	50	5735720	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	9	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120076	899	0	0	0	0	0	120053	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120033	1	1	20021	10	9	10	10010	10000	10	10000	0	0	186	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120078	899	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120039	899	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120033	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	99	0	1270	1	16	1	0	119574	10000	10000	10000	10010	120033	120033	120033	120033	120036
30024	120032	899	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	18	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 3: throughput

Count: 8

Code:

  dup v0.16b, w8
  dup v1.16b, w8
  dup v2.16b, w8
  dup v3.16b, w8
  dup v4.16b, w8
  dup v5.16b, w8
  dup v6.16b, w8
  dup v7.16b, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3351

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	200	1	1	0	0	2	26697	0	25	160100	100	80000	80000	100	80020	80015	500	1169557	1883252	0	26693	26708	26708	6636	6	6657	160136	200	80024	80024	200	80020	80020	26883	26768	1	1	80201	100	99	100	100	80000	100	80000	1	0	153	2	1	1	1	5119	8	16	3	8	26987	80000	80000	100	26709	26709	26709	26709	26709
160204	26800	200	1	1	132	88	2	26858	0	25	160100	100	80000	80000	100	80020	80375	500	1168951	1887370	0	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	129	0	1	1	1	5119	3	16	8	3	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26715	200	1	1	0	0	2	26693	0	25	160100	100	80000	80000	100	80020	80016	500	1168951	1884163	0	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	174	0	1	1	1	5119	6	16	6	6	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	0	2	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1897326	0	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	0	1	1	1	5119	8	16	3	8	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	0	2	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1888889	0	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	78	0	1	1	1	5119	8	16	8	8	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	0	2	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1892932	0	26689	26708	26708	6634	6	6661	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	3	0	1	1	1	5119	8	16	8	8	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	0	2	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1886310	0	26689	26708	26708	6632	6	6657	160135	200	80216	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	0	1	1	1	5119	3	16	8	8	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	0	2	26693	0	25	160100	100	80000	80000	100	80208	80196	500	1168951	1892340	0	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	0	1	1	1	5119	8	16	8	8	26705	80000	80000	100	26864	26719	26718	26709	26709
160204	26875	200	1	1	0	108	2	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168956	1884163	0	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26711	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	63	0	1	1	1	5119	8	16	9	8	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26814	201	1	1	0	0	2	26693	0	25	160100	100	80000	80000	100	80020	80016	500	1170128	1884163	0	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	63	0	1	1	1	5119	6	16	8	8	26705	80000	80000	100	26709	26709	26709	26709	26709

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26708	199	2	2	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	10	9	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26782
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	13	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26780
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80370	80000	50	1183832	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	120	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26809
160024	26710	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168868	1883014	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	123	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26711	26712	26738
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6690	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	12	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26755
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	33	80000	10	3	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26774
160024	26710	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	19	3	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26812
160024	26716	199	0	0	26693	25	160010	10	80000	80000	10	80555	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	129	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26795
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	6	111	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26787
160024	26710	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1170361	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	25	3	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26798

DUP (general, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations