Firestorm: DUP (general, 2D) measurements

Code:

  dup v0.2d, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	75	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	378	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	376	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	6	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	377	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	377	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	379	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	378	391	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	15	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.2d, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120034	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13678201	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	1	3	0	1328	1	2	24	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120034
30204	120032	899	0	0	0	12	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120014	120032	120032	115528	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	4	0	1	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109479	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13678206	1	120013	120073	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	1	0	0	0	0	120017	109456	25	40126	10100	20000	10000	100	20000	10000	500	5735672	13679094	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	3	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120038	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13678855	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	36	0	1312	1	2	16	2	2	119577	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	102	20000	10000	500	5735672	13683257	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120076	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	0	9	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	0	120013	0	120032	120032	115548	3	116264	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	0	2	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1296	0	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	0	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10002	10	20000	10000	50	5735672	13670029	0	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	0	3	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	15	0	1270	0	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1272	0	1	16	1	1	119574	10000	10000	10000	10010	120034	120033	120033	120033	120033
30024	120032	899	0	0	3	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	5	120013	0	120032	120090	115548	3	116262	30012	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	5	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120074	120077
30024	120032	899	0	0	0	120017	109456	38	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	5	120013	0	120032	120067	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	5	3	16	3	2	119574	10002	10000	10000	10010	120033	120033	120033	120033	120071
30024	120068	900	1	0	0	120017	109456	25	40010	10010	20000	10002	10	20000	10000	50	5738120	13670820	0	0	120013	0	120032	120032	115549	3	116262	30180	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	5	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109497	25	40010	10010	20000	10000	10	20000	10000	60	5735681	13670090	1	5	120013	0	120032	120032	115547	3	116262	30179	20	10000	20000	20	10000	20000	120032	120108	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	5	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 3: throughput

Count: 8

Code:

  dup v0.2d, x8
  dup v1.2d, x8
  dup v2.2d, x8
  dup v3.2d, x8
  dup v4.2d, x8
  dup v5.2d, x8
  dup v6.2d, x8
  dup v7.2d, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	200	0	0	26693	5	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	1	1	1	5117	0	17	0	0	26705	80000	80000	100	26724	26709	26709	26709	26709
160204	26708	200	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1882981	0	26698	26713	26709	6630	9	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	1	0	2	2	2	5127	1	24	1	1	26706	80000	80000	100	26720	26717	26710	26710	26710
160204	26709	201	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	1	26690	26709	26709	6621	9	6644	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5127	1	24	1	1	26706	80000	80000	100	26718	26714	26718	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	1	26690	26709	26709	6621	9	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5128	1	24	1	1	26706	80000	80000	100	26727	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	1	26690	26709	26709	6621	9	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5128	1	24	1	1	26706	80000	80000	100	26710	26714	26715	26723	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	0	26690	26709	26709	6621	9	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5128	1	24	1	1	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	1	26690	26709	26709	6621	10	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5127	1	24	1	1	26706	80000	80000	100	26828	26711	26718	26712	26710
160204	26709	200	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	0	26690	26709	26709	6621	9	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5127	1	24	1	1	26706	80000	80000	100	26718	26710	26715	26710	26710
160204	26709	199	0	0	26694	0	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	0	26690	26709	26709	6621	9	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5127	1	24	1	1	26706	80000	80000	100	26710	26710	26710	26710	26710
160204	26709	200	0	0	26694	5	25	160100	100	80000	80000	100	80023	80018	500	1168352	1883460	0	26690	26709	26709	6621	9	6645	160141	200	80023	80023	200	80023	80023	26709	26709	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	2	2	2	5127	1	24	1	1	26706	80000	80000	100	26710	26710	26711	26710	26710

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26714	200	1	0	1	12	2	26697	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	17	16	0	13	15	26705	80000	80000	10	26717	26709	26709	26709	26709
160024	26708	200	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	30	16	0	19	13	26705	80000	80000	10	26710	26709	26709	26709	26709
160024	26813	200	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	1	0	5022	15	16	0	16	13	26705	80000	80000	10	26714	26717	26709	26718	26709
160024	26708	200	1	0	2	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	14	16	0	15	12	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	15	16	0	12	15	26705	80000	80000	10	26709	26709	26711	26709	26709
160024	26708	200	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80178	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	13	16	0	16	12	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	199	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	16	16	0	14	15	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	12	16	0	13	11	26705	80000	80000	10	26832	26711	26717	26709	26709
160024	26708	200	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	12	16	0	15	12	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	1	0	1	0	2	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5022	12	16	0	15	13	26705	80000	80000	10	26709	26709	26709	26709	26709

DUP (general, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations