Firestorm: DUP (general, 2S) measurements

Code:

  dup v0.2s, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	357	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	376	376	376	376
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	493	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	383	381	376	381
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	358	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	381	376	379	376
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	379	376	379	376
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	381	376	379	376
2004	375	3	1	1	0	2	360	0	25	2000	1033	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	376	376	376	376
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	363	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	3	75	5	16	5	5	372	1000	1000	376	376	378	376	376
2004	375	2	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	23022	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	381	376	376	376
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	357	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	376	376	376	376
2004	375	3	1	1	0	2	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	365	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	75	5	16	5	5	372	1000	1000	376	376	376	376	376

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.2s, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120034	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5736176	13672053	1	120013	120032	120032	115525	3	116298	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	2	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672164	1	120013	120032	120032	115525	3	116302	30100	200	10000	20000	200	10000	20000	120032	120032	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120018	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116294	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116249	30100	202	10000	20000	200	10000	20000	120032	120032	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	6	0	0	1310	1	3	25	3	5	119574	10000	10000	10000	10100	120033	120033	120130	120036	120034
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116312	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120079	120035	115525	3	116304	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	4	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120069	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672386	1	120018	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116312	30125	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120035	120298	120197	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	0	105	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120016	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	861	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	2	16	1	1	119637	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	786	120018	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115548	3	116316	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	2	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	885	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	1	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	882	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	9	116269	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	822	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120114	120038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120038
30024	120032	899	0	0	390	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120041	120033	120033	120033
30024	120032	900	0	0	555	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	954	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	831	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116463	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 3: throughput

Count: 8

Code:

  dup v0.2s, w8
  dup v1.2s, w8
  dup v2.2s, w8
  dup v3.2s, w8
  dup v4.2s, w8
  dup v5.2s, w8
  dup v6.2s, w8
  dup v7.2s, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26710	200	0	1	72	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26822	26724	27094	6642	6	6673	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26716	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26811	26717	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26786	26719	26717	6648	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	15	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26805	26708	26735	6652	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26689	26708	26871	6721	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26827	27352	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26818	26717	26713	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	206	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26808	26721	26714	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26805	26716	26718	6634	6	6657	160135	200	80020	80020	200	80020	80020	26708	26711	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	26757	26714	26717	6647	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26713	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26758	26800	26710	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	3	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26758	26710	26712	6657	0	3	6695	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	2	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26778	26782	26708	6658	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26847	26717	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26877	26716	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26757	26714	26717	6667	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	12	1	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26893	6659	89	3	6691	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	12	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1888565	1	26754	26708	26722	6672	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26751	26715	26717	6666	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26762	26715	26715	6663	0	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709

DUP (general, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations