Firestorm: DUP (general, 4H) measurements

Code:

  dup v0.4h, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	373	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	3	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	110	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	360	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22901	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	377	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	379	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	9	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	377	375	72	3	108	2000	1000	1000	1000	1000	379	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.4h, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120032	899	0	336	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	798	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120016	0	120035	120032	115533	3	116244	30100	202	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	1353	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	1119	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	2	16	2	2	119651	10000	10000	10000	10100	120033	120033	120033	120033	120034
30204	120032	899	0	117	0	120017	109456	25	40100	10100	20000	10000	100	20117	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	9	0	1	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	1224	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	993	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	3	16	2	2	119574	10000	10000	10000	10100	120035	120033	120033	120033	120033
30204	120032	899	0	1335	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120072
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	2	16	2	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	966	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120028	0	120032	120068	115527	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115688	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	3	16	3	2	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120040	120296	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	4	16	2	2	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	15	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120014	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	3	0	0	1270	4	16	2	2	119579	10000	10000	10000	10010	120377	120035	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	4	0	0	1270	2	16	3	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109459	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	2	119574	10000	10000	10000	10010	120033	120033	120033	120033	120034
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	4	16	1	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	1	1	15	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120015	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20131	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10064	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	3	16	2	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30177	20	10000	20000	20	10000	20000	120038	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	2	3	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 3: throughput

Count: 8

Code:

  dup v0.4h, w8
  dup v1.4h, w8
  dup v2.4h, w8
  dup v3.4h, w8
  dup v4.4h, w8
  dup v5.4h, w8
  dup v6.4h, w8
  dup v7.4h, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	199	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1881588	0	26691	0	26720	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	1	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26700	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26689	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	199	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26699	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80130	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26719	26709	26709	26709	26709
160204	26717	200	24	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26689	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26694	0	26710	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26698	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26698	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26689	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26698	0	26708	26708	6632	0	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	1	1	1	5117	0	16	26705	80000	80000	100	26709	26709	26709	26709	26709

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26710	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1171272	1888997	1	26693	26712	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	4	16	5	3	26705	80000	80000	10	26709	26709	26715	26713	26709
160024	26710	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1161239	1913473	1	26692	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26711	26711	1	1	80021	10	9	10	10	80000	10	0	80000	0	871	5020	3	16	3	2	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26700	27	25	160010	10	80000	80000	10	80000	80000	50	1173741	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	2	16	2	3	26705	80000	80000	10	26709	26709	26709	26709	26713
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1176619	1888030	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	2	16	2	3	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26697	2	25	160010	10	80000	80000	10	80000	80000	50	1177429	1885056	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	5	16	5	3	26705	80000	80000	10	26709	26709	26709	26713	26709
160024	26708	200	0	26800	0	25	160010	10	80000	80000	10	80000	80000	50	1173018	1884287	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	6	16	5	6	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1171514	1889796	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	5	16	2	3	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1169624	1889972	1	26689	26708	26708	6653	3	6688	160010	20	80214	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	2	16	2	3	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1171266	1887523	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	3	16	3	3	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1171323	1888790	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	80000	0	0	5020	3	16	5	3	26705	80000	80000	10	26709	26709	26709	26709	26709

DUP (general, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations