Firestorm: DUP (general, 4S) measurements

Code:

  dup v0.4s, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	375	3	0	361	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	376	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22898	1	356	375	375	72	3	108	2000	1000	1192	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	379	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	361	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	1	3	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	380	72	3	108	2000	1000	1000	1000	1000	378	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	377	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	1	0	73	1	16	1	1	372	1000	1000	379	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	380	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	3	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	378	376	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	3	73	1	16	1	1	372	1000	1000	376	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	112	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	1	16	1	1	372	1000	1000	376	376	376	376	376

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.4s, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10050	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	1	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120101	120038	120033	120033	120033
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	3	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120093	120036	120033	120033	120033
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20132	120060	120034	1	1	20201	100	99	100	10100	10000	100	10000	0	0	177	0	0	0	1310	1	2	16	2	2	119643	10000	10000	10000	10100	120033	120033	120033	120046	120033
30204	120072	899	0	0	675	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	3	120032	120032	115525	3	116240	30100	200	10000	20000	200	10065	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120034	120033	120033
30204	120033	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	3	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10067	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120066	120036	120033	120033	120033
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	3	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120017	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119577	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1	0	1309	1	16	1	1	119589	10000	10000	10000	10010	120033	120121	120118	120033	120287
30024	120252	900	12	120020	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735768	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	34	1	1	119806	10000	10000	10000	10010	120210	120033	120033	120033	120034
30024	120035	899	12	120020	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670257	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120034	120040	1	1	20021	10	9	10	10010	10000	10	10000	4	2	0	0	0	1270	1	16	1	1	119656	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	120017	109456	25	40018	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	119620	10000	10000	10000	10010	120041	120034	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10014	20004	10000	10	20000	10000	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	119631	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	119596	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	119643	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	12	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10001	0	0	18	0	0	1270	1	16	1	1	119637	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	119643	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	204	120017	109456	25	40010	10010	20000	10000	10	20000	10050	50	5735672	13670029	0	0	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	24	0	0	1270	1	16	1	1	119579	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 3: throughput

Count: 8

Code:

  dup v0.4s, w8
  dup v1.4s, w8
  dup v2.4s, w8
  dup v3.4s, w8
  dup v4.4s, w8
  dup v5.4s, w8
  dup v6.4s, w8
  dup v7.4s, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26710	200	1	1	0	26693	12	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	973	1	1	1	5117	2	16	1	1	26840	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26710	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26711	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26713	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26820	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	1	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26711	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	2	1	26778	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26705	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	21	26696	0	25	160360	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26711	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26817	0	80000	80000	100	26709	26709	26709	26713	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26713	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	0	80000	0	1	1	1	5117	1	16	1	1	26821	0	80000	80000	100	26709	26709	26709	26709	26709

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	a9	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	199	0	0	26697	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	4	16	0	0	4	4	2	26804	0	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	1	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80133	0	0	5020	0	0	0	9	16	0	0	4	3	4	26851	0	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5024	0	0	0	4	16	0	0	4	4	2	26726	0	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80214	26760	26732	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	4	16	0	0	4	7	4	26708	0	80000	80000	10	26709	26712	26709	26709	26709
160024	26708	200	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	4	16	0	0	4	4	2	26711	0	80000	80000	10	26709	26819	26927	26712	26709
160024	26708	200	9	0	26697	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	2	16	0	0	5	4	2	26715	0	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	4	16	0	0	4	4	4	26710	0	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	5	16	0	0	4	2	4	26713	0	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	2	16	0	0	4	2	4	26711	0	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	1	26689	0	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	5020	0	0	0	4	16	0	0	3	2	4	26837	0	80000	80000	10	26709	26709	26709	26709	26709

DUP (general, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations