Firestorm: DUP (general, 8B) measurements

Code:

  dup v0.8b, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	ac	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	361	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	394	377	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	379	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	380	375	1	1	1001	1000	1000	0	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	3	73	0	1	16	0	1	1	372	1000	1000	376	376	376	376	376

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.8b, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120032	899	1	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120017	120032	120032	115525	3	116240	30100	200	10000	20000	200	10061	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	4	16	2	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	1	0	12	0	120017	109456	25	40100	10100	20000	10000	100	20113	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	3	119576	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	1310	1	2	16	2	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	3	16	3	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120035	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	102	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	9	1310	1	2	16	3	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	12	88	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	1310	1	2	16	3	2	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109457	25	40133	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	3	3	119574	10002	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	202	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10005	0	0	0	1310	1	3	16	2	3	119574	10000	10000	10000	10100	120033	120116	120037	120033	120033
30204	120033	899	0	0	0	0	0	0	0	120017	109493	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	24	1310	1	3	16	2	2	119579	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	1	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120034	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120033	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120068	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	3	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	12	20000	10000	50	5737040	13670480	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	120032	120032	115550	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	2	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115564	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	22490	1295	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	3	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 3: throughput

Count: 8

Code:

  dup v0.8b, w8
  dup v1.8b, w8
  dup v2.8b, w8
  dup v3.8b, w8
  dup v4.8b, w8
  dup v5.8b, w8
  dup v6.8b, w8
  dup v7.8b, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26709	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26822	26850	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26711	80000	80000	100	26739	26709	26709	26711	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26829	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5140	0	16	0	0	26720	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26912	26742	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26772	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26711	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26844	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26706	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26689	26711	26708	6632	6	6657	160505	200	80020	80020	200	80020	80020	26708	26769	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26814	80000	80000	100	26715	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26761	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26717	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26776	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	0	0	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26793	1	1	80201	100	99	100	100	80000	100	80000	0	0	0	1	1	1	5117	0	16	1	0	26705	80000	80000	100	26709	26709	26709	26709	26709

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	ac	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26708	199	9	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26714	26771	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	6	3	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6655	3	6688	160010	20	80000	80000	20	80000	80000	26711	26708	2	1	80021	10	9	10	10	80000	10	80000	0	0	5020	6	1	16	1	1	26710	80000	80000	10	26709	26713	26709	26889	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26714	26804	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	6	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	201	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26711	26716	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	6	2	16	1	1	26717	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	5	1	16	1	1	26713	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	6	26713	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26798	26716	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	6	2	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	1	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26711	26709	5	1	80021	10	9	10	10	80000	10	80000	0	0	5020	6	1	16	1	2	26711	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26713	26799	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	6	2	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26711	26714	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	4	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26714	1	1	80021	10	9	10	10	80000	10	80000	0	1	5020	4	2	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709

DUP (general, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations