Firestorm: DUP (general, 8H) measurements

Code:

  dup v0.8h, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	358	375	375	72	3	108	2000	1000	1000	1000	1000	380	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	377	1	1	1001	1000	1000	1	0	73	2	16	1	2	372	1000	1000	391	379	376	376	376
2004	376	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	3	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	375	2	0	360	0	25	2000	1000	1000	1000	1000	14291	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	457	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	25128	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	1	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	375	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	375	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376
2004	380	3	0	360	0	25	2000	1000	1000	1000	1000	14075	22820	0	356	375	406	72	3	108	2000	1000	1000	1000	1000	375	375	1	1	1001	1000	1000	0	0	73	2	16	2	2	372	1000	1000	376	376	376	376	376

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.8h, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120093
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	3	16	3	4	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	1	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	13	0	0	1310	1	4	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120036	120033
30204	120032	899	0	0	0	0	606	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	20	0	0	1310	1	4	16	5	6	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116246	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109458	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115529	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	11	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	3	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	899	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	20000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	4096	0	1310	1	4	16	3	3	119574	10000	10000	10000	10100	120033	120033	120033	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120064	0	120032	120032	115548	3	116262	30010	20	10124	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10004	0	2	0	0	0	1270	6	16	1	1	119620	10006	10000	10000	10010	120211	120033	120036	120118	120033
30024	120032	899	18	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670259	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10006	4	2	3963	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120035	120034	120034	120033
30024	120033	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735720	13670029	0	120013	0	120112	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	3	0	0	1270	1	16	1	1	119689	10000	10000	10000	10010	120033	120033	120034	120033	120035
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	2	1	119574	10000	10000	10000	10010	120033	120037	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735768	13670029	0	120013	0	120032	120032	115548	3	116293	30010	20	10000	20000	20	10000	20000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	2	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120068	115548	3	116262	30010	20	10000	20000	20	10000	20000	120370	120032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1296	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10004	10	20472	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120047	120034	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1270	3	16	1	2	119575	10000	10000	10000	10010	120034	120033	120035	120373	120035
30024	120037	899	0	120017	109463	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670713	0	120016	0	120032	120032	115548	3	116269	30010	20	10000	20000	20	10000	20000	120061	120033	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120034	120034	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120060	120033	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	899	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	20000	120035	120035	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	119574	10000	10000	10000	10010	120033	120033	120033	120033	120033

Test 3: throughput

Count: 8

Code:

  dup v0.8h, w8
  dup v1.8h, w8
  dup v2.8h, w8
  dup v3.8h, w8
  dup v4.8h, w8
  dup v5.8h, w8
  dup v6.8h, w8
  dup v7.8h, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26710	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168326	1884163	1	26693	0	26708	26713	6632	6	6657	160136	200	80020	80020	202	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	2	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	199	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	0	26708	26708	6632	6	6657	160136	200	80020	80020	204	80020	80020	26715	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	0	26708	26708	6632	6	6657	160136	200	80020	80024	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26689	0	26708	26708	6632	6	6657	160136	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	0	26708	26708	6632	6	6657	160136	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	0	26689	0	26708	26708	6632	6	6657	160135	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	0	26710	26708	6632	6	6657	160135	200	80024	80024	200	80020	80020	26717	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	0	26708	26708	6632	6	6657	160136	200	80024	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26712	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	0	26708	26708	6632	6	6657	160134	200	80020	80020	200	80020	80020	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	200	1	1	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1884163	1	26689	0	26708	26708	6632	6	6657	160136	200	80024	80020	200	80020	80024	26708	26708	1	1	80201	100	99	100	100	80000	100	80000	1	1	1	5117	1	16	1	1	26705	80000	80000	100	26709	26709	26709	26709	26709

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26709	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6741	160010	20	80000	80000	20	80000	80000	26709	26723	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	14	16	12	9	26705	80000	80000	10	26718	26709	26709	26709	26709
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	9	16	11	6	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80567	80000	20	80000	80000	26712	26764	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	10	16	12	11	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6825	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	10	16	11	11	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26725	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	11	16	11	9	26709	80000	80000	10	26709	26709	26711	26719	26709
160024	26708	221	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	9	16	10	7	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	1	26689	26708	26708	6653	24	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	12	16	10	12	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6758	160010	20	80759	80000	20	80000	80000	26712	26714	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	12	16	11	12	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	199	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6688	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	13	16	12	12	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	26693	25	160010	10	80000	80000	10	80000	80000	50	1168880	1884032	0	26689	26708	26708	6653	3	6740	160010	20	80000	80000	20	80000	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5020	11	16	11	9	26811	80000	80000	10	26709	26732	26709	26709	26709

DUP (general, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations