Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

EOR (vector, 8B)

Test 1: uops

Code:

  eor v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110008073116111787100020382038203820382038
1004203716096116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100002773116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100004873116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  eor v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000228061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000001030071011611197910100001002003820038200382003820085
102042003715000000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000000147196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000000450196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000030071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000001000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476802001820037200371842203187451010020010000200200002003720037111020110099100100100001000003000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119687200212510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001006640316221978510000102003820038200382003820038
100242003715006119687025100101010000101000050284768020018200372003718444031876710010201000020200002003720037111002110910101000010170640216221978510000102003820038200382003820038
100242003715018611968702510010101000010100005028476802001820085200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968702510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968702510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968702510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
10024200371500821968702510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001013640216221978510000102003820038200382003820038
10024200371500611968702510010101000010100005028476802001820037200371844403187671001020100002020338200372003711100211091010100001000640216221978510000102008620038200382003820038
10024200371500611968702510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968702510010101000010100005028476802001820037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  eor v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000030710122411197910100001002003820038200382003820086
10204200371501101471968725101001051001210010000618284896312001820037201331842203187451027120010000204203322003720086211020110099100100100001001000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000012710152500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000000710011611197915100001002003820038200382003820038
10204200371500021611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001002200710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842203187621010020010000200200002003720037111020110099100100100001000000710011611197910100001002003820038200382003820038
1020420037150010611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000000710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318193f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500010519687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500094319687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000102006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000102006402162219785010000102003820038200382003820038
10024200371500016619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102022820038200382003820038
10024200371500012619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500016819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000103006402162219785010000102003820038200382003820038
1002420037149006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500012419687251001010100001010000502847680020018200852003718444318767100102010000202000020037200371110021109101010000101006401162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  eor v0.8b, v8.8b, v9.8b
  eor v1.8b, v8.8b, v9.8b
  eor v2.8b, v8.8b, v9.8b
  eor v3.8b, v8.8b, v9.8b
  eor v4.8b, v8.8b, v9.8b
  eor v5.8b, v8.8b, v9.8b
  eor v6.8b, v8.8b, v9.8b
  eor v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150010325801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000511041645200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000511031634200350800001002003920039200392003920039
802042003814904025801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000511041645200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000511041654200350800001002003920039200392003920039
802042003815008225801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000511041644200350800001002003920039200392003920039
8020420038150059925801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000511031654200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100100511031643200350800001002003920039200392003920039
8020420038150012825801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100200511031644200350800001002003920039200392003920039
8020420038150010325801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000511041645200350800001002003920039200392003920039
802042003815006125801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100100511031644200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001050208164420035080000102003920039200392003920039
800242003815000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001050206163320035080000102003920039200392003920039
800242003815021039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001050205164420035080000102003920039200392003920039
800242003815000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001050204162220035080000102003920039200392003920039
800242003815500060258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001050204162320035080000102003920039200392003920039
8002420038150000514258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001050205162320035080000102003920039200392003920039
800242003815000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001050205162220035080000102003920039200392003920039
800242003815400039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001050205163420035080000102003920039200392003920039
800242003815000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001050205164420035080000102003920039200392003920039
800242003815000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001050204162220035080000102003920039200392003920039