Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

EXT (vector, 16B)

Test 1: uops

Code:

  ext v0.16b, v0.16b, v1.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371504861168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371501261168725100010001000264680201820372037157231895100010002000203720371110011000073116111830100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150361168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150361168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371502461168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720731110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  ext v0.16b, v0.16b, v1.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150002081968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842503187451010020010000204206622008520037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000037101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010310000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000020640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500012119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000001640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ext v0.16b, v1.16b, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715045611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715024611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715001561968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715075611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150210761968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715030611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715027611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150275361968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371490611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715090611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006403162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150003631968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000206402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ext v0.16b, v8.16b, v9.16b, #3
  ext v1.16b, v8.16b, v9.16b, #3
  ext v2.16b, v8.16b, v9.16b, #3
  ext v3.16b, v8.16b, v9.16b, #3
  ext v4.16b, v8.16b, v9.16b, #3
  ext v5.16b, v8.16b, v9.16b, #3
  ext v6.16b, v8.16b, v9.16b, #3
  ext v7.16b, v8.16b, v9.16b, #3
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150004025801001008000010080000500640000020019200382003899733100228010020080000200160000200382003811802011009910010080000100511031611200350800001002003920039200392003920039
802042003815006402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
802042003815006402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
8020420038150167052580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100511011711200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)dfe0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915001452580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100018502265164222003580000102003920039200392003920039
800242003815001452580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100024502262162422003580000102003920039200392003920039
800242003815001425258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502262162422003580000102003920039200392003920039
80024200381500145258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502264164422003580000102008920039200392003920039
80024200381500145258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502264162422003580000102003920039200392003920039
80024200381500145258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502264162422003580000102003920039200392003920039
80024200381500145258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502264164222003580000102003920039200392003920039
800242003815001330258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502262164422003580000102003920039200392003920039
80024200381500145258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502262164422003580000102003920039200392003920039
80024200381500145258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502264164222003580000102003920039200392003920039