Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FABD (scalar, D)

Test 1: uops

Code:

  fabd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220000612548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037221000612548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230000612548251000100810003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372300720612548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230000612548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037220000612548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230000612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372300988612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372310870612548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372300001562548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  fabd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225366129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373008411102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225336129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830085300383003830038
1020430037225516129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722566129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722566129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161130034100001003003830038300383003830038
1020430037225458229530251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722436129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722566129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225610529548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640716222963010000103003830086300853008430038
10024300372252461295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010600640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372261861295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372242461295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225661295482510010101000010100005042786703001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fabd d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500961295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225003061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250018346295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000371011611296340100001003003830038300383003830038
102053003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000251295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500661295482510100100100001001014850042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830085300383003830038
1020430037225000536295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037225961295482510010101000010100005042777970300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037225661295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037224061295482510010101000010100005042773131300183003730037282873287671001020100002020340300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037224061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372252461295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372251561295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fabd d0, d8, d9
  fabd d1, d8, d9
  fabd d2, d8, d9
  fabd d3, d8, d9
  fabd d4, d8, d9
  fabd d5, d8, d9
  fabd d6, d8, d9
  fabd d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060151724125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020092200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915064125802211008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200392180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915028523125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815003402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000050204165520036080000102004020040200402004020040
8002420039150012402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000050205164320036080000102004020040200402004020040
800242003915009402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001020050204164420036080000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050205163320036080000102004020040200402004020040
800242008815000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050204164520036080000102004020040200402004020040
80024200391500129222580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050204273420036080000102004020040200402004020040
8002420039150015402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050203164320036080000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050204165520036080000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020160000200392003911800211091010800001000050205163420036080000102004020040200402004020040
8002420039150001032580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050203163420036080000102004020040200402004020040