Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FABD (vector, 4S)

Test 1: uops

Code:

  fabd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372301262548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372381612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037233612548251000100010003983133018303730372415328951000100023223037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372302902548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372302802548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723241052548251000100010003983133018303730372415328951000100020003037303711100110003073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000373116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  fabd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722509173295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021611296340100001003003830038300383003830038
102043003722503961295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250661295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250661295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250661295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
102043003722504261295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000171011611296340100001003003830038300383003830038
1020430037225036061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250661295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037224029461295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250661295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722401050612954825100101010000101000050427731313001830037300372829632876710010201000020200003003730037111002110910101000010000000640316222963010000103003830038300383003830038
10024300372250510612954825100371010000101000050427731313012630037300372828732884210010201000020200003003730037111002110910101000010000000640716222963010000103003830038300383003830038
100243003722503601032954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000400640216222963010000103003830038300383003830038
10024300372250270612954825100101010000101000065427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000100661216222963010000103003830038300383003830038
10024300372250007262954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250540612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250120612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
10024300372250240612954825100101010000101000050427867013005430037300372829232876710010201000020200003003730037111002110910101000010041030665216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fabd v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250108061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250210103295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100003071011611296340100001003003830038300383003830038
1020430037225033061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225025510861295482510100100100001001000050042773130300183003730085282650328745101002001000020020000300373003711102011009910010010000100120071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282650328745101002001000020420000300373007911102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225021061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225036061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830085
102043003722501288652295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100020071011611296340100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403163329630010000103003830038300383003830038
100243003722502761295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006403173129630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fabd v0.4s, v8.4s, v9.4s
  fabd v1.4s, v8.4s, v9.4s
  fabd v2.4s, v8.4s, v9.4s
  fabd v3.4s, v8.4s, v9.4s
  fabd v4.4s, v8.4s, v9.4s
  fabd v5.4s, v8.4s, v9.4s
  fabd v6.4s, v8.4s, v9.4s
  fabd v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051103162220036800001002004020040200402004020040
8020420039150041258010010080000100800005006400002002020039200399973399978010020080000200160000200392003911802011009910010080000100180051103162220036800001002004020040200402004020040
8020420039150015225801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010040051102162220036800001002004020040200402004020040
8020420039150124125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102162220036800001002004020040200402004020040
802042003915004125801001008000010080000500640000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102162220036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500154025800101080000108000050640000312002020039200399996310019800102080000201600002003920039118002110910108000010000050206164420036080000102004020040200402004020040
8002420039150004025800101080000108000050640000512002020039200399996310019800102080213201606282019620142318002110910108000010004760050203164320036080000102004020040200402004020040
8002420039149004025800101080000108000050640000412002020039200399996310019800102080000201600002003920039118002110910108000010000050203164320036080000102004020040200402004020040
8002420039150204025800101080000108000050640000312002020039200399996310019800102080000201600002003920039118002110910108000010000050203163420036080000102004020040200402004020040
8002420039150204025800101080000108000050640000312002020039200399996310019800102080000201600002003920039118002110910108000010000050203164320036080000102004020040200402004020040
8002420039150004025800101080000108000050640000312002020039200399996310019800102080000201600002003920039118002110910108000010000050934164420036080000102004020040200402004020040
8002420039150004025800101080097108000050640000412002020039200399996310019800102080000201600002003920039118002110910108000010000050204163420036080000102004020040200402004020040
8002420039150004025800101080000108000050640000312002020039200399996310019800102080000201600002003920090118002110910108000010000050204163420036080000102004020040200402004020040
80024200391500124025800101080000108000050640000312002020039200399996310019800102080000201600002003920039118002110910108000010000050204164420036080000102004020040200402004020040
8002420039150204025800101080000108000050640000312002020039200399996310019800102080000201600002003920039118002110910108000010000050204164320036080000102004020040200402004020040