Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FABS (vector, 2D)

Test 1: uops

Code:

  fabs v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371606116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100007073116111786100020382038203820382038
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000002473116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037211001100000073116111786100020382038203820382038
100420371606116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521201820372037157131895100010001000203720371110011000001873116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000673116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fabs v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)a9cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500961196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037211020110099100100100001000000171011611197910100001002003820038200382003820038
102042003715002194196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001002000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000010071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197911100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371500061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000906119686251001010100001010000502847521120019200372003718443318767100102010000201000020037200371110021109101010000104000000006402162219786010000102003820038200382003820038
100242003715000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000000006402162219786010000102003820038200382003820038
100242003715000006119686251002210100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000100006402162219786010000102003820038200382003820038
1002420037150000053619686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000000006402162219786010000102003820038200382003820038
100242003715000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000000006402162219786010000102003820038200382003820038
100242003715000006119686451002513100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000000006402162219786010000102003820038200382003820038
100242003715000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006006402162219786010000102003820038200382003820038
100242003715000006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000000006402162219786010000102003820038200382003820038
100242003715000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000000006402162219786010000102003820038200382003820038
100242003715000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fabs v0.2d, v8.2d
  fabs v1.2d, v8.2d
  fabs v2.2d, v8.2d
  fabs v3.2d, v8.2d
  fabs v4.2d, v8.2d
  fabs v5.2d, v8.2d
  fabs v6.2d, v8.2d
  fabs v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150302925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039
8020420038150002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000111511801620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915038125800101080000108000050640000412001920038200389996310018800102080000208000020038200381180021109101080000100150200416112008680000102003920039200392003920039
8002420038150939258001010800001080000506400004120019200382003899962510018800102080000208000020038200381180022109101080000100050202116112003580000102003920039200392003920039
8002420038150183925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100050200216222003580000102003920039200392003920039
800242003815003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100050200216212003580000102003920039200392003920039
800242003815003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100050200116112003580000102003920039200392003920039
800242003815033925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100050200116112003580000102003920039200392003920039
800242003815003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100050200116112003580000102003920039200392003920039
800242003815093925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100050200116112003580000102003920039200392003920039
800242003815003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100050440116112003580000102003920039200392003920039
800242003815003925800101080000108000050640000012001920038200389996310018800102080000208000020038200381180021109101080000100050200116112003580000102003920039200392003920039