Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FABS (vector, 2S)

Test 1: uops

Code:

  fabs v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073216111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037160611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100001273116111786100020382038203820382038
100420371515611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110002073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fabs v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007103161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010664200372003711102011009910010010000100107101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100027101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715012419686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003751102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521020065200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371496119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150010319686251001010100001010000502847521020018200372003718443318767103172010000201050620037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201050420037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150025119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000642216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715008419686251001010100001010000502847521020018200372003718443318767100102010489201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
1002420037150027919686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fabs v0.2s, v8.2s
  fabs v1.2s, v8.2s
  fabs v2.2s, v8.2s
  fabs v3.2s, v8.2s
  fabs v4.2s, v8.2s
  fabs v5.2s, v8.2s
  fabs v6.2s, v8.2s
  fabs v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150101302925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151184161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151181161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000003011151181161120035800001002003920039200392003920039
8020420038150101009225801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000211151181161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151181161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151181161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151181161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151181161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151181161120035800001002003920039200392003920039
8020420038150101002925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000000011151181161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020216112003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381502739258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381509514258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381501539258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381507539258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
8002420038150939258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381501244258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010005020116112003580000102003920039200392003920039