Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FACGE (vector, 2S)

Test 1: uops

Code:

  facge v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110002073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371600611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000973116111787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100001873116111787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100002173116111787100020382038203820382038
100420371500611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715001261687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  facge v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038
102042003715001950611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038
10204200371500001051968725101161001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000001710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038
10204200371500720611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038
102042003715001560611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011621197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155106119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100306402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718448318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382013420038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500010519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500010319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500994319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715002886119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000101006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  facge v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010001571011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150361196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001004071011611197910100001002003820038200382003820038
1020420037150066196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150361196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011612197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715010000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006404162219785210000102003820038200382003820038
100242003715010000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000120232196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006422242219785010000102003820038200382003820038
10024200371501111297104626196872510012121000010100005028476801200182003720037184443187671001220100002020000200372003711100211091010100001000006402163319785010000102003820038200382003820038
100242003715000000061196872510010101000012100006028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000001206119687251001210100001210000602847680120018200372003718444318767100102010000202000020037200371110021109101010000100011706404162219785010000102003820038200382003820038
1002420037150000012061196872510010101000010100005028476801200182003720037184443187671001220100002020000200372003711100211091010100001000006422162319785010000102003820038200382003820038
100242008515000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715010000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000006061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001001006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  facge v0.2s, v8.2s, v9.2s
  facge v1.2s, v8.2s, v9.2s
  facge v2.2s, v8.2s, v9.2s
  facge v3.2s, v8.2s, v9.2s
  facge v4.2s, v8.2s, v9.2s
  facge v5.2s, v8.2s, v9.2s
  facge v6.2s, v8.2s, v9.2s
  facge v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200481510040258010010080000100800005006400000200192003820038997303999680125200800002001600002003820038118020110099100100800001000511031611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000511211611200350800001002003920039200392003920039
80204200381500040258012510080000100800005006400000200192003820038997303999680125200800002001600002003820038118020110099100100800001000511011611200350800001002003920039200392003920039
80204200381490040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000511011611200350800001002003920039200392003920039
8020420038150022840258010010080000100800005006400000200192003820038997303999580125200800002001600002003820038118020110099100100800001000511011611200350800001002003920039200392003920039
80204200381500084258010010080000100800005006400000200192003820038997303999680125200800002001600002003820038118020110099100100800001000511221611200350800001002008820039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000511031732200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000511011611200350800001002003920039200392003920039
802042003815001540258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000511211611200350800001002003920039200392003920039
8020420038150020740258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502001416131720035080000102003920039200392003920039
800242003815003925800101080000118000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100502001116121420035080000102003920039200392003920039
80024200381500392580010108000010801125064000002001920038200389996310018800102080000201600002003820038118002110910108000010050200916101520035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100502001116161320035080000102003920039200392003920039
80024200381502043925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100502001516141420035080000102003920039200392003920039
8002420038150183925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502001216111120035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100502001216131620035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010050200151613920035080000102003920039200392003920039
800242003815003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100502001216161320035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100502001516121320035080000102003920039200392003920039