Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FACGT (scalar, S)

Test 1: uops

Code:

  facgt s0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203716008416872510001000100026468012018203720371572318951000100020002037203711100110002020073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715008216872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  facgt s0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150258611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715024611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715024611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371503611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371509611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150381611968725101001001000010010000500284768012001820037200371842231876410100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371502461196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316221978510000102003820038200382003820038
10024200371507561196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715040561196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150361196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371501861196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150961196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371501561196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150661196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037149061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  facgt s0, s1, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000051611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119855100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000012310000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500009611968725101001001000010010000500284768012001820085200841842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820086200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119859100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020101692020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  facgt s0, s8, s9
  facgt s1, s8, s9
  facgt s2, s8, s9
  facgt s3, s8, s9
  facgt s4, s8, s9
  facgt s5, s8, s9
  facgt s6, s8, s9
  facgt s7, s8, s9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150274025801001008000010080000500640000200192003820038997339996801002008000020016000020090200381180201100991001008000010000508051103161120035800001002003920039200392003920039
8020420038150082258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100200051101161120035800001002003920039200392003920039
8020420038150940258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920112200392008720039
80204200381502440258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100009051101161120073800001002003920039200392003920039
802042003815016240258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381501261258010010080000100800005046400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101162120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015002103925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020121610620035080000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020101661020035080000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020101610620035080000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020101661020035080000102003920039201112003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020101661020035080000102003920039200392003920039
80024200871500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020101661020035080000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010502061610620035080000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020616101020035080000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000105020101610620035080000102003920039200392003920039
800242003815000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001050201116101020035080000102003920039200392003920039