Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FACGT (vector, 2D)

Test 1: uops

Code:

  facgt v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382085
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716010316872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  facgt v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000097101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000487101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500276119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000067101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000067101161119791100001002003820038200382003820038
1020420037150006119687451010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000097101161119791100001002003820038200382003820038
102042003715001561196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000847101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000111640316221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715002461196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100090640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500636119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000180640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  facgt v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002371011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002115671011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001008071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001003371011611197910100001002003820038200382003820038
10204200371500024061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001009071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001003371011611198570100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476801200182003720037184223187451026520010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000061196762510100100100001001000055628476801200182003720037184223187451010020010000200200002003720037211020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001030640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671016420100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  facgt v0.2d, v8.2d, v9.2d
  facgt v1.2d, v8.2d, v9.2d
  facgt v2.2d, v8.2d, v9.2d
  facgt v3.2d, v8.2d, v9.2d
  facgt v4.2d, v8.2d, v9.2d
  facgt v5.2d, v8.2d, v9.2d
  facgt v6.2d, v8.2d, v9.2d
  facgt v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051106161120035800001002003920039200392003920039
8020420038150000011282580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100020051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000005152580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000351101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200316232003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100650200216242003580000102003920039200392003920039
800242008915000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200316322003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000101050200216222003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200316222003580000102003920039200392003920039
8002420038150001022580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200416322003580000102003920039200392003920039
8002420038150001022580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200316222003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039
8002420038150001022580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200316112003580000102003920039200392003920039
8002420038150005092580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050200116112003580000102003920039200392003920039