Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FACGT (vector, 4S)

Test 1: uops

Code:

  facgt v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715008216872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000673216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110001373216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000373216221787100020382038203820382038
10042037150016416872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110001073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  facgt v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000336119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000671011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000371011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500001956119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000034619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715096119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100316403160221978510000102003820038200382003820038
1002420037150336119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038
1002420037150053619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038
10024200371503516119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402161221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402160221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  facgt v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500661968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842203187631027520010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000307101161119827100001002003820038200382003820038
102042003715005361968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371506611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000001561968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000090611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000090611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000060611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000090611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037149000000611968725100101010000101000050284768012001802003720037184563187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000000006403163319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  facgt v0.4s, v8.4s, v9.4s
  facgt v1.4s, v8.4s, v9.4s
  facgt v2.4s, v8.4s, v9.4s
  facgt v3.4s, v8.4s, v9.4s
  facgt v4.4s, v8.4s, v9.4s
  facgt v5.4s, v8.4s, v9.4s
  facgt v6.4s, v8.4s, v9.4s
  facgt v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511031611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011612200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020089200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011601200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200850800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997325999680100200800002001600002003820038118020110099100100800001001126511011612200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500063258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500001239258001010800001280000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000502011169122003580000102003920039200392003920039
8002420038150000055625800101080000108000050640000020019200382003810005310018800102080000201600002003820038118002110910108000010105020121611112003580000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020121611122003580000102003920039200392003920039
8002420038150000243925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100155020121612122003580000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020131612132003580000102003920039200392003920039
80024200381490000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010095020121611122003580000102003920039200392003920039
80024200381501000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010065020111611112003580000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010035020131613112003580000102003920039200392003920039
80024200381500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020111612122003580000102003920039200392003920039
800242003815000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100125020131611122003580000102003920039200392003920039