Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FADDP (scalar, H)

Test 1: uops

Code:

  faddp h0, v0.2h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722000612547251000100010003981600301830373037241432895100010002000303730371110011000073216332629100030383038303830383038
1004303723000612547251000100010003981600301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
10043037230039822547251000100010003981600301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
1004303723000612547251000100010003981600301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
1004303723000612547251000100010003981601301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
10043037230001562547251000100010003981601301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
1004303723000612547251000100010003981600301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
1004303724000612547251000100010003981601301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
1004303723000612547251000100010003981601301830373037241432895100010002000303730371110011000073316332629100030383038303830383038
1004303723003612547251000100010003981600301830373037241432895100010002000303730371110011000073316332629100030383038303830383038

Test 2: Latency 1->2

Code:

  faddp h0, v0.2h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003722500191295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001001007101161129633100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101163129633100001003003830038300383003830038
10204300372250061295474310120100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372240061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003722500441295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
1002430037225000361295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010106402162229629010000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010006401162229629010000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500027726295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010007262162229629010000103003830038300383003830038
1002430037225000061295472510010101000010100005042771603006530037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250000726295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250000726295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250000536295472510010101000010100005042771603001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250000251295474410010101000010100005042785123001830037300372828632876710010201000020200003003730037111002110910101000010006402242229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  faddp h0, v8.2h
  faddp h1, v8.2h
  faddp h2, v8.2h
  faddp h3, v8.2h
  faddp h4, v8.2h
  faddp h5, v8.2h
  faddp h6, v8.2h
  faddp h7, v8.2h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420049150930258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039218020110099100100800001000111511823300200360800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
8020420039150030258010810080008100800205006401321200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
802042003915035430258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
80204200391501830258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
80204200391501830258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040
8020420039150030258010810080008100800205006401320200202003920039997706999080120200800322001600642003920039118020110099100100800001000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915002704025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502000516442003680000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100100502000216242003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502000316242003680000102004020040200402004020040
800242003915002404025801081080000108000050640000020030200392003999968100468001020800002016000020039200391180021109101080000102100502000416242003680000102004020040201032010220040
800242008915020888225800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502000216242003680000102004020040200402004020040
800242003915003904025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100030502000216252003680000102004020040200402004020040
800242003915003906325800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502000216242003680000102004020040200402004020040
800242003915001204025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000503800429422003680000102004020040200402004020040
800242003915000884025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502011216442003680000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502000416242003680000102004020040200402004020040