Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FADDP (vector, 4H)

Test 1: uops

Code:

  faddp v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037231102682548251000100010003983131301830373037241532895100010002000303730371110011000077416442630100030383038303830383038
100430372211022582548251000100010003983130301830373037241532895100010002000303730371110011000077416442630100030383038303830383038
100430372311212682548251000100010003983130301830373037241532895100010002000303730371110011000077416442630100030383038303830383038
1004303722116626825482510001000100039831303018303730372415328951000100020003037303711100110001277416442630100030383038303830383038
10043037231102682548251000100010003983130301830373037241532895100010002000303730371110011000077416442630100030383038303830383038
10043037241102682548251000100010003983130301830373037241532895100010002000303730371110011000077416442630100030383038303830383038
10043037231102682548251000100010003983130301830373037241532895100010002000303730371110011000077416442630100030383038303830383038
10043037231102682548251000100010003983130301830373037241532895100010002000303730371110011000077416442630100030383038303830383038
10043037231102682548251000100010003983130301830373037241532895100010002000303730371110011000377416442630100030383038303830383038
10043037231102682548251000100010003983131301830373037241532895100010002000303730371110011000077416442630100030383038303830383038

Test 2: Latency 1->2

Code:

  faddp v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722510061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500061295482510110100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250001422295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225000149295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225000166295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722400061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383008630038
10204300372250001081295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001001007331161329667100001003003830132300383018330085
102043003722500061295482510115100100001051014950042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225000618295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001001007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225682295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722402236295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037225084295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830086
10024300372250187295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250145295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250187295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250145295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372240145295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250166295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038
10024300372250145295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  faddp v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500361295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722400582295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500187295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500168295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830087
102043003722500187295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001001071021622296340100001003003830038300383003830038
1020430037225001662954825101001001000010010000500427731313001830037300372826525287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722400103295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038
102043003722500145295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383008530038
102043003722500208295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225010329548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225012429548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225012429548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402492229630010000103003830038300383003830038
1002430037225036929548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722408229548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037224017029548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225016629548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225021229548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100066402162229630010000103003830038300383003830038
1002430037225012429548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225016629548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300853003830038

Test 4: throughput

Count: 8

Code:

  faddp v0.4h, v8.4h, v9.4h
  faddp v1.4h, v8.4h, v9.4h
  faddp v2.4h, v8.4h, v9.4h
  faddp v3.4h, v8.4h, v9.4h
  faddp v4.4h, v8.4h, v9.4h
  faddp v5.4h, v8.4h, v9.4h
  faddp v6.4h, v8.4h, v9.4h
  faddp v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915100004125801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100000511031611200360800001002004020040200402004020040
802042003915001004125801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
802042003915000004125801001008000010480000500640000120100200392003999830399978022920080000200160212200392003911802011009910010080000100002511011611200366800001002004020040200402004020097
80204200391500001084125801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100000511011611200360800001002004020040200402004020040
8020420039150001204125801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100100511011611200360800001002004020040200402004020040
802042003915000008325801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100100511011611200360800001002004020040200402004020040
802042003915000004125801001008000010080000500640000020020200392003999730399978010020080000200160000200392003911802011009910010080000100190511011611200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
800242003915003352580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
800242003915003692580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000010200202003920039999631001980010208000020160000200392003911800211091010800001000502000116112003680000102004020040200402004020040