Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FADDP (vector, 4S)

Test 1: uops

Code:

  faddp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230010325482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110004073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722606125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  faddp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102161129634100001003003830132300383003830038
1020430037225061295482510100100100001001000061842773130300183003730037282653287451010020010000200200003003730037111020110099100100100001004007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003008530038300383003830038
1020430037225061295482510100100100001001000052642773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
10024300372250000000072629548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383008530038
1002430037225000000006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010149504277313300183003730037282873287671001020100002020000300373003711100211091010100001000000006402162229630010000103003830038300383003830038
1002430073227011076804616330329485141100661110056141029877428545530270303193031828315282889510908201116720219523036430366811002110910101000010203121929507873722429880310000103036930370303673036930407
1002430367228010167795264493429485139100721510064131044770428681230306303683008528316322887811054241100022219643037030368711002110910101000010022121948807652563329881110000103036730370304083013330367

Test 3: Latency 1->3

Code:

  faddp v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020530037225000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037224000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037225000000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037224000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
1020430037224000000006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03090e191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250100612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000640316222963010000103003830038300383003830038
100243003722500008332954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828703287671001020100002020000300373003711100211091010100001003640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427867003001830037300372828703287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  faddp v0.4s, v8.4s, v9.4s
  faddp v1.4s, v8.4s, v9.4s
  faddp v2.4s, v8.4s, v9.4s
  faddp v3.4s, v8.4s, v9.4s
  faddp v4.4s, v8.4s, v9.4s
  faddp v5.4s, v8.4s, v9.4s
  faddp v6.4s, v8.4s, v9.4s
  faddp v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500030258010810080008100800205006401320200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401321200200200392016799876999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
802042003915000505258010810080008100800205006401321200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200203200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401320200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040
80204200391500030258010810080008100800205006401321200200200392003999776999080120200800322001600642003920039118020110099100100800001000111511816020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500008225800101080000108000050640000120063200392003999963100198001020800002016000020039200391180021109101080000100050203163220036080000102004020040200402004020040
8002420039150000272448001010800001080107506400001200202003920039999631001980010208000020160000200392003911800211091010800001011250202163320036080000102004020040200402009220040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050203163320036080000102004020040200402009020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000101350203163320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050203163320036080000102004020040200402004020040
800242003915000013525800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050203163320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050203162320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100950202163320036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120070200392003999963100198001020800002016000020039200391180021109101080000100050203163320036080000102004020040200402004020040
800242003915000124025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000101050202163320036080000102004020040200402009120040