Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FADD (scalar, D)

Test 1: uops

Code:

  fadd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723038225482510001000100039831303018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004308423008425482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112702100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230017025482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220015625482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  fadd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500892954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225001032954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225007262954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101321129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303006530037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001021000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295482510010101000010100005042773133001830037300372829932876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003017930037111002110910101000010010640316332963010000103003830038300383003830038
10024300372370061295482510010101000010100005042773133001830037300372828732884210010201000020200003003730037111002110910101000010010640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250061295392510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000724316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
100243003722503961295482510010101000010100005042773133001830180300372829232876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038
10024300372250061295482510010101000010100005042773133001830037300372828732876710010201000020200003003730037111002110910101000010000640316332963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fadd d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722539612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003008530038300383003830038
10204300372240612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300802250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101160229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010007101161129634100001003003830038300383003830038
1020430037225072629548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100967101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250002542954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018330037300372830232876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731330018030037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fadd d0, d8, d9
  fadd d1, d8, d9
  fadd d2, d8, d9
  fadd d3, d8, d9
  fadd d4, d8, d9
  fadd d5, d8, d9
  fadd d6, d8, d9
  fadd d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150110248258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000511411161212200360800001002004020040200402004020040
8020420039150110248258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000511412161212200360800001002004020040200402004020040
8020420039150110248258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000511412161212200360800001002004020040200402004020040
802042003915011024825801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100000051141216810200360800001002004020040200402004020040
802042003915011024825801001008000010080000500640000120020200392003999730399978010020080000200160000200392003911802011009910010080000100000051141016105200360800001002004020040200402004020040
8020420039150110290258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000511412161210200360800001002004020040200402004020040
80204200391501102482580100100800001008000050064000012002020039200399973039997801002008000020016000020039200391180201100991001008000010000005114121688200360800001002004020040200402004020040
8020420039150110248258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000511412161210200360800001002004020040200402004020040
80204200391501102134258010010080000100800005006400001200202003920039997303999780100200800002001600002003920039118020110099100100800001000000511481688200360800001002004020040200402004020040
80204200391501102482580100100800001008000050064000012002020039200399973039997801002008000020016000020039200391180201100991001008000010000005114101688200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)dbddfetch restart (de)dfe0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815002502580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326031603382003680000102004020040200402004020040
800242003915002732580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326021603382003680000102004020040200402004020040
800242003915002502580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326031604382003680000102004020040200402004020040
800242003915002502580010108000010801075664082001200202003920039999631001980010208000020160000200392003911800211091010800001000050326021612382003680000102004020040200402004020040
800242003915002502580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326041604482003680000102004020040200402004020040
800242003915002502580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326031603282003680000102004020040200402004020040
8002420039150021172580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326021603382003680000102004020040200402004020040
800242003915002502580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326031603382003680000102004020040200402004020040
800242003915002502580010108000010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326041603382003680000102004020040200402004020040
800242003915002502580010108008010800005064000001200202003920039999631001980010208000020160000200392003911800211091010800001000050326031602382003680000102004020040200402004020040