Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FADD (scalar, H)

Test 1: uops

Code:

  fadd h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372211026825482510001000100039831313018303730372415328951000100020003037303711100110000077316442630100030383038303830383038
100430372211026825482510001000100039831313018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372311026825482510001000100039831303018303730372415328951000100020003037303711100110000377416442630100030383038303830383038
100430372311026825482510001000113939831313018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
1004303722116211025482510001000100039831303018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372311026825482510001000100039831303018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372211026825482510001000100039831313018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
1004303723110211225482510001000100039831313018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372311026825482510001000100039831313018303730372415328951000100020003037303711100110000077416442630100030383038303830383038
100430372311026825482510001000100039831313018303730372415328951000100020003037303711100110000077416442630100030383038303830383038

Test 2: Latency 1->2

Code:

  fadd h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000017101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007321161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372251861295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001010640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037224061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225025229548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000104412640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fadd h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000006312954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020530037224000001562954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250000072629548251010010010000100100005004277313030018300373003728265122874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000810010000500427731303001830037300372826532874510100200100002002036030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372251061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250061295482510010121000012100006042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250061295482510019131000010100005042773130300183003730037282870328767100102010000202000030037300371110021109101010000100006402242229630010000103003830038300383003830038
10024300372240061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250961295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372251061295482510010101000010100005042773131300183003730037282870328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fadd h0, h8, h9
  fadd h1, h8, h9
  fadd h2, h8, h9
  fadd h3, h8, h9
  fadd h4, h8, h9
  fadd h5, h8, h9
  fadd h6, h8, h9
  fadd h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815004125801001008000010080000500640000120020200392003999893999780100200800002001600002003920039118020110099100100800001000511041611200360800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
80204200391503214125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
80204200391502464125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000513611611200360800001002004020040200402004020040
802042003915004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
80204200391504234125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000511011611200360800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010005110116112003625800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facc2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150003340258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001002502009166102003680000102004020040200402004020040
8002420039150000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010005020010161062003680000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010005020010161062003680000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010005020010166102003680000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010005020010161062003680000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010005020010161062003680000102004020040200402004020040
800242003915000124025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050380101610102003680000102004020040200402004020040
8002420039150011261258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001030502007161272003680000102010020040200402004020040
8002420039150109402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010005020310161062003680000102004020040200402004020040
8002420039150000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010005020061610102003680000102004020040200402004020040