Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FADD (vector, 4H)

Test 1: uops

Code:

  fadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073216112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303722014725482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430852306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372206125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372396125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372308225482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
100430372306125482510001000100039831330183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  fadd v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200203323003730037111020110099100100100001000015227947101161029634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000000127101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005974277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101161129634100001003003830038300383003830038
1020430037225006129548831010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000001007101161129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000007101160129634100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000001007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)d8ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000100064021602229630010000103003830038300793003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201032220200003003730037111002110910101000010000000064021602229630010000103003830038300383003830038
100243003722511003532954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000064021602229630010000103003830038300383003830038
1002430037225012101242954825100101010000101000050427731303001830085300852828732876710010201000020200003003730037111002110910101000010030000064021602229630010000103003830038300383008530038
10024300372250090612954825100101010024101000050427731303001830037300372828732878610010201000022200003003730037211002110910101000010000000064021602229668010000103003830038300383003830038
10024300372250090612954825100101010000101000050427731303001830037300372828772878610010201000020200003003730037111002110910101000010001100064021603229918010000103003830038300383003830038
100243003722500001582954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000004064021602229630010000103003830038300383003830038
10024300372250000612954825100101010008101000050427731313001830037300372829232878510010201016120200003003730037111002110910101000010000030064021602229630010000103003830085300383003830038
10024300372251000612954825100101110000101000050427731313001830037300832828732876710010201000020200003003730037111002110910101000010000000064021602229630010000103003830085300863003830038
10024300372250000612954825100101010000101014960427731303001830037300372828732876710010201000020203243003730037111002110910101000010000000064021602229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fadd v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372251106129548251010010010000100100005004277313030018300373003728272628741101002001000820020016300373003711102011009910010010000100001117181161129650100001003003830038300383003830038
10204300372241106129548251010010010000100100005004277313130018300373003728272628741101002001000820020016300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204303252260006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300853003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001036402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731323001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
100243003722407262954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731313001803003730037282873287671001020100002020000300373003711100211091010100001006402162229630110000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fadd v0.4h, v8.4h, v9.4h
  fadd v1.4h, v8.4h, v9.4h
  fadd v2.4h, v8.4h, v9.4h
  fadd v3.4h, v8.4h, v9.4h
  fadd v4.4h, v8.4h, v9.4h
  fadd v5.4h, v8.4h, v9.4h
  fadd v6.4h, v8.4h, v9.4h
  fadd v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051102161120036800001002004020040200402004020040
80204200391500232258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000109800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500115258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400000200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500129258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150016625800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502015161014200360080000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502015161613200360080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502013161212200360080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502015161813200360080000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100000502016161313200360080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502016161613200360080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502011161115200360080000102004020040200402004020040
8002420039150042025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502011161613200360080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100000502011161416200360080000102004020040200402004020040
80024200391500402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010000050201216118200360080000102004020040200402004020040