Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FADD (vector, 4S)

Test 1: uops

Code:

  fadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
1004303722132612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112659100030383038303830383038
10043037226612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
100430372275612548251000100010003983130301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
1004303723195612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037220612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038
100430372354612548251000100010003983131301830373037241532895100010002000303730371110011000000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  fadd v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071021611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240000612954825100101010000101000050427867013001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300842250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
100243003722500009432954825100101010000101000050427731303001830037300372830732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fadd v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225010329548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102161129634100001003003830038300383003830038
102043003722506129548251010010010000100101495004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225012429548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225012429548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225012429548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225012429548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225043129548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225018729548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383008530038
102043003722506129548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225093929548251010010010000100100005004277313300183003730037282650328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000082295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250000145295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037224000061295394410010101000010100005042773131300183008330037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037225000661295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000661524222966810000103003830038300383003830038
100243003722500012103295482510010101000010100005042773131300183003730037282878287671001020101682020000300373003721100211091010100001000000640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300843003711100211091010100001000001640216222963010000103003830038300383003830038
10024300372250000145295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
1002430037224000061295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250001261295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038
10024300372250001261295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fadd v0.4s, v8.4s, v9.4s
  fadd v1.4s, v8.4s, v9.4s
  fadd v2.4s, v8.4s, v9.4s
  fadd v3.4s, v8.4s, v9.4s
  fadd v4.4s, v8.4s, v9.4s
  fadd v5.4s, v8.4s, v9.4s
  fadd v6.4s, v8.4s, v9.4s
  fadd v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150101000261825801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051141116911200360800001002004020040200402004020040
802042003915010100025125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051141116119200360800001002004020040200402004020040
80204200391501010002823258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511491699200360800001002004020040200402004020040
802042003915010100025125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039218020110099100100800001000051141116911200360800001002004020040200402004020040
8020420039150101000251258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511491677200360800001002004020040200402004020040
802042003915010100022402580100100800001008000050064000012002020039200399973399978010020080000200160000200392003911802011009910010080000100005114101694200360800001002004020090200402004020040
8020420039150101000251258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010013511441647200360800001002004020040200402004020040
802042003915010100025125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000051149161111200360800001002004020040200402004020040
8020420039150101000272258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511481649200360800001002004020040200402004020040
8020420039149101000293258010010080000100800005006400001200202003920039997339997801002008000020016000020039200391180201100991001008000010000511471699200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015010402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200516772003680000102004020040200402004020040
800242003915000612580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200616672003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200616672003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200416562003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200516652003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200816562003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200716982003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200716562003680000102004020040200402004020040
800242003915000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010050200716882003680000102004020040200402004020040
800242003915000402580010108000010800005064000002007020039200399996310019800102080000201600002003920039118002110910108000010050200516752003680000102004020040200402004020040