Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCADD (vector, 2D)

Test 1: uops

Code:

  fcadd v0.2d, v0.2d, v1.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723082254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
100430372321661254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037220254254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723061254825100010001000398313130183037303724153289510001000200030373037111001100001073216222630100030383038303830383038

Test 2: Latency 1->2

Code:

  fcadd v0.2d, v0.2d, v1.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372240013258008229548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728276328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225000000010329548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300713003830038
1020430037224000000024129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100027837101162129668100001003003830038300383003830084
102043003722501000006129548251010010010000100100005004277313130018300373003728265328745105792001032820020000300373013211102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250011932954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000300640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225001682954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710160201000020200003003730037111002110910101000010000001640216222963010000103003830038300383003830038
100243003722400612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
1002430037225003462954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640216222963010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  fcadd v0.2d, v1.2d, v0.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
102043003722500186612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
10204300372250012612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
10204300842250006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710316222963421100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010030071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773131300183003730037282873287671001024100002020000300373003711100211091010100001000000640316432966810000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372240000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316132963010000103003830038300383003830038
100243003722500000443295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000000640316332963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  fcadd v0.2d, v8.2d, v9.2d, #90
  fcadd v1.2d, v8.2d, v9.2d, #90
  fcadd v2.2d, v8.2d, v9.2d, #90
  fcadd v3.2d, v8.2d, v9.2d, #90
  fcadd v4.2d, v8.2d, v9.2d, #90
  fcadd v5.2d, v8.2d, v9.2d, #90
  fcadd v6.2d, v8.2d, v9.2d, #90
  fcadd v7.2d, v8.2d, v9.2d, #90
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039150041258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051103161120036800001002004020040200402004020040
802042003915001742258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500923258010010080000100800005006400002007102003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400002002002003920039997339997801002008000020016021020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
80204200391500516258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020040200402004020040
8020420039150041258010010080000100800005006400002002002003920039997339997801002008000020016000020039200391180201100991001008000010000051101161120036800001002004020093200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915000000096258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205165520036080000102004020040200402004020040
80024200391500000001043258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000450205164520036080000102004020040200402004020040
800242003915000000074258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205165420036080000102004020040200402004020040
800242003915000000068258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205164520036080000102004020040200402004020040
800242003915000000068258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205165420036080000102004020040200402004020040
800242003915000000068258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205165420036080000102004020040200402004020040
800242003915000000068258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000006050205165420036080000102004020040200402004020040
800242003915000000068258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205165520036080000102004020040200402004020040
800242003915000000068258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050204165420036080000102004020040200402004020040
800242003915000000068258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000010050205164520036080000102004020040200402004020040